DS90LV804: Max skew among the LVDS pairs over multiple chips

The maximum propagation delay is the maximum, i.e., it cannot be increased further.

Due to the buffering inside the chip, there is a pipeline effect, i.e., the input can change even when the output has not yet finished switching. 800 Mbps signals are guaranteed to be transmitted correctly.

When you have multiple devices in parallel, the maximum skew between any two channels is 1.1 ns. At 800 Mbps, the pulse length is 1.25 ns. So with multiple devices, the maximum usable rate is about 400 Mbps.

thank for the answer Clemens, I see your point. 

I am also wondering, since the delay is stated typically 2ns, does it mean it can be less than that? In example, one chip could have the delay of cca 1ns while the other chip could have the max stated 3.2ns, what means the skew of 2.2ns. How about that possibility?

Hi Pero,

The characterization data comes from testing a large pool of devices and using statistical values to determine the set values for min, nom, and max in the recommended operating conditions. This means that some of the devices may have lower skew. However, some devices (the outliers of a select device pool) may have up to the maximum value in skew. When creating a "skew budget" for your design, you can factor this thought process in. Ultimately, you must determine how much "risk" you are willing to tolerate, knowing that it is highly unlikely all four of the buffers will have the maximum worse case skew mentioned above. There is also the possibility that the FPGA can add delay taps if the skew is too large once designed.

Thank you, Amy

thank you for the reply Amy.

Unfortunately, I have to plan for the maximum possible skew that chould theoretically happen, and I am taking board skew as well as the FPGA skew in consideration.

I would be very thankful if you could help me out estimating maximum skew accross the 16 pairs, that is, 4 DS90LV804 buffers. 

My thought process so far is:

There is also a setup and hold times from the FPGA receiver but they are within ps range, but i am neglecting them at the moment.

The DS90LV804 skew happens to be the bottleneck here, and effectively limits my datarate to 1/(2.3 + 0.16) = 400 Mbps.

How reasonable would you say my estimation is?

Delay and skew are different things. You cannot combine them.

If the four buffer chips use the same V_CC and have the same temperature, then the maximum skew is 1.1 ns. If they have different temperatures, then the skew could be larger (and there is no specified value). But is there any reason to assume that the temperatures would be different?

As far as I can see, your total skew is 1.1 ns + 160 ps = 1.26 ns, which would correspond to the pulse length of a 793 Mbps signal, so your usable speed is somewhat lower.

Thanks for the answer, Clemens! I appreciate your time and effort to look into the topic.

I would gladly take 1.1ns estimation as a max skew among the chips, but I would love to have an explanation first:

Delay and skew are different things. You cannot combine them.

Why couldnt I combine them? The delay is statistically distributed accross the multiple values, with mean being 2ns and max 3.2ns. It seems to me like this distribution is what contributes to the skew among the chips. Would you care to explain this a bit further?

The skew is the difference between the maximum and the minimum delay.

But you cannot compute the skew by substracting the typical delay from the maximum delay, and then adding again the chip-to-chip skew. The skew is already included in the delay maximum (although you don't know the minimum), and these values have different test conditions.

Hi Pero,

Let me check into this and I will get back to you next week.

Thank you, Amy

so the skew estimatition accounts for the delay differences among the chips? That's why you said earlier that (given the same power supply and temperature), no channel will be skewed more than 1.1ns across the multiple chips on board?

Yes, the part-to-part skew accounts for the differences between any channels of any chips.

Hi Pero,

I am OOO this week, I will get back to you no later than 7/19/24.

Thank you, Amy

no worries. Wish you well in your absence

HI Pero,

Thank you very much. Before then, here is a helpful resource on part-to-part skew (page 2) 

Defining Skew,Propagation-Delay,Phase Offset (Phase Error)

I will get back to you soon. -Amy

Hi Pero,

These parameters can be viewed as derivatives of each other, which I believe is what your understanding has been all along. The worst case skew (from a TI device perspective, not including other system skew sources) will then be 1.1 ns +/- 125 ps.

Regards, Amy

Hello Amy, thank you for the detailed answer. I gave it a thought and I must say it contradicts something that @Clemens has mentioned earlier.

In your analysis you are adding 3.2ns delay to each chip, ending with max 12.8ns propagation delay, which is something that doesnt sit well with me. 3.2 ns is max delay, no matter how many chips do we put on the plate. Having 12.8+0.5+6.6 = 20ns inherent skew would make this buffer practically useles in any backplane applications that are operating above 50 MHz, which is something really hard do believe.

Now, the skew is another topic  - Clemens said that no matter how many chips do we have the max skew among them is 1.1ns. And this is something deduced from the max propagation delay. He said specifically that skew can not be simply added into the propagation delay for the budget estimation. So, I decided to take his word and plan 1.1ns as a max skew over entire 4 chips on my board.

Hi Pero,

Thank you for checking on this. I will double check this with a systems-level LVDS expert to confirm.

I am just returning from being out of office, please give me a few days to get back to you.

Thank you, Amy

sure, no worries! Thank you for your effort

You are welcome, thank you for your patience.

-Amy

Hey Amy thanks for staying with me on this topic! Okay, this is something I can get my head around. 

I see that you have added 125 ps of channel-to-channel skew to the base 1.1 ns of inter-chip skew. How is that so? Is it not in this case that one is again the derivative of another?