Tool/software:
Hi experts,
I'm using DPB3867IR in my design, RGMII is being used, and a FPGA is used as the controller.
Please refer to below for the waveform I captured inside FPGA.
- The sample clock is 100MHz;
- MDIO pin is an inout signal for FPGA, when MDIO output is high, FPGA will drive it; when low, it's input for FPGA;
- MDIO input is also sampled,
- PHY reset signal is an output of FPGA.
After PHY reset signal has been de-asserted (high), and MDIO output enable is still high, as there is an 2.2k pull-up in my board, MDIO should be high, while it is low for some time, it looks like the PHY is driving MDIO.
When this happened, my controller can't access PHY resistor, I mean I can still drive MDC/MDIO, but PHY would always reply zero.
This error will happen in 50% chance, when MDIO is high during MDIO output enable is high, the PHY can be accessed normally, can you give me some suggestion?
Regards
Chris
