DP83867IR: DP83867 Ethernet 100Base-T SI issue

Hi Snow!

I'm glad that you were able to resolve your compliance issue with our troubleshooting guide! Please find my replies below.

Q1:

The best place would be in the dp83867_config_init() function. This is a long function where mainly the MAC interface is confirmed and configured, but the register write can be set towards the end of the function. When the driver is loaded, this function will be among the first to run.

As a test:

• add the register write in this function, boot the board, and read 0xA0 on the terminal to confirm if the value is what you set.
• If the previous step was successful, change the value of 0xA0 from the terminal
• run ifconfig ethx down and inconfig ethx up and read Reg 0xA0 from the terminal again
  • This will reload the driver, the expected output should be what you had set in the driver

Q2:

During manufacturing, there is a desired setting for A0, but the "tuning knob" is different between each part. Meaning, two different parts can be on the same setting (in this case that setting is the Register value) and have different outputs. We want the output to be the same, so the die is "trimmed", meaning that the default values may differ between parts. Search for "trim parameters" online for more information.

Q3:

Reg 0x170 controls the output of the CLKOUT pin, this has no effect on the MDI portion of the PHY.

Regards,

Alvaro

Hi Alvaro

Thank you very much for your help, I tried to modify the dp86837 driver to configure the TXG_GAINSEL_FINE parameter. Can you help me see if this patch is suitable?

```

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-anvet.dts b/arch/arm64/boot/dts/freescale/imx8mp-anvet.dts
index efeb3a4e84b9..ca7dc8962f56 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-anvet.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-anvet.dts
@@ -718,6 +718,11 @@ &pmic {
/delete-property/ interrupts;
};

+/* custom ANA_LD_TXG_FINE_GAINSEL_AB */
+&ethphy0 {
+ ti,txg-gain-sel-fine = /bits/ 16 <0x0609>;
+};
+
&pwm2 {
status = "okay";
};
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 5f08f9d38bd7..f2b1df0c2ecd 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -44,6 +44,7 @@
#define DP83867_STRAP_STS1 0x006E
#define DP83867_STRAP_STS2 0x006f
#define DP83867_RGMIIDCTL 0x0086
+#define DP83867_ALTFGAB 0x00A0
#define DP83867_DSP_FFE_CFG 0x012c
#define DP83867_RXFCFG 0x0134
#define DP83867_RXFPMD1 0x0136
@@ -153,6 +154,9 @@
/* FLD_THR_CFG */
#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7

+/* ALTFGAB bits */
+#define DP83867_ALTFGAB_MASK (GENMASK(3, 0) | GENMASK(11, 8))
+
#define DP83867_LED_COUNT 4

/* LED_DRV bits */
@@ -193,6 +197,8 @@ struct dp83867_private {
bool set_clk_output;
u32 clk_output_sel;
bool sgmii_ref_clk_en;
+ u16 txg_gain_sel_fine;
+ bool set_txg_gain_sel;
};

static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -683,6 +689,14 @@ static int dp83867_of_init(struct phy_device *phydev)
return -EINVAL;
}

+ /* Read ALTFGAB config, if not set, keep default */
+ if (!of_property_read_u16(of_node, "ti,txg-gain-sel-fine",
+ &dp83867->txg_gain_sel_fine)) {
+ dp83867->set_txg_gain_sel = true;
+ } else {
+ dp83867->set_txg_gain_sel = false;
+ }
+
return 0;
}
#else
@@ -946,6 +960,12 @@ static int dp83867_config_init(struct phy_device *phydev)
mask, val);
}

+ /* Update TXG_GAINSEL_FINE if it is set */
+ if(dp83867->set_txg_gain_sel) {
+ phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_ALTFGAB,
+ DP83867_ALTFGAB_MASK, dp83867->txg_gain_sel_fine);
+ }
+
return 0;
}

```

I tested this code according to your steps, and the configuration can be set successfully.

An additional question is:

Does this chip have a command or tool to modify the value of the 0x00A0 register during the production phase, so that the driver does not need to modify its value during the run phase?

Regards

Snow

HI Alvaro

Thank you for your support!

Regards,

Snow