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Original question:

[FAQ] LMH0397: HD PLL Pathological Bit Error

LMH0397: HD PLL Pathological Bit Error

Conor
Guru 12115 points
Part Number: LMH0397

Tool/software:

Hi,

According to the FAQ, it is mentioned that ConfigIO Reg 0x22 = 0x28 needs to be set as a countermeasure against SDI pathological signal errors.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1037296/faq-lmh0397-hd-pll-pathological-bit-error

However, the above is not mentioned in the latest datasheet, and I am wondering if it is really necessary. At the moment, the IC works without any problems even when a pathological signal is input. Do you have any comments?

Thanks,

Conor

  • 0
    TI__Guru* 93670 points

    Hi Conor,

    This recommendation was made based on a customer report and test instrument used. It is up to you to whether implement this or not. We haven't had any negative feedback so you can decide to implement this as well.

    Regards, Nasser

  • 0 in reply to Nasser Mohammadi
    Guru 12115 points

    Hi Nasser,

    Thank you for your reply.

    I'd like to know one more thing. When I extend the input cable length, a CRC error sometimes occurs when I observe the output signal on a waveform monitor.

    For example, a CRC error occurs when I extend it to about 220M on HD, but if I turn off the LMH0397 reclocker, no errors occur in the output signal even if I extend the input cable to about 250M.

    The cable equalizer is functioning properly, but the reclocker seems to come off sometimes. If you know anything about how to deal with this, please let me know. The likely cause is a power supply S/N problem, but are there any other solutions such as hidden registers?

    Thanks,

    Conor

  • 0 in reply to Conor
    TI__Guru* 93670 points

    Hi Conor,

    It is possible switching power supply could be causing or injecting noise into the supply. I am not aware of register settings that can fully attenuate this jitter being added to the CDR loop filter.

    Regards, Nasser

  • 0 in reply to Nasser Mohammadi
    Guru 12115 points

    Hi Nasser,

    FAQ says "To prevent this occurrence. we can force rate detector to stay at HD/3G rate," but what should I set if an SD signal is received? Should I set it to the initial value of "0X00"?

    When I write data 0x28 to address 0x22 on the Share Register Page, it appears to work without any problems even when an SD signal is input. The data sheet says address 0x22 is reserved, so I'm confused about what setting I should make to it.

    Thanks,

    Conor

  • 0 in reply to Conor
    TI__Guru* 93670 points

    Hi Conor,

    At SD data rate this issue was not observed. This was observed at HD only. So you do not need to do anything at SD. At SD data rate this register is not used. This register is used only for HD/3G.

    Regards, Nasser

  • 0 in reply to Nasser Mohammadi
    Guru 12115 points

    Hi Nasser,

    Thank you for your reply.

    If I set the data 0x28 to address 0x22 once, is there no need to rewrite the setting depending on the input signal? Or do I need to reset the setting when an SD signal is input?

    Incidentally, we have confirmed that making this setting when inputting HD-SDI has an effect on pathology signals.

    Thanks,

    Conor

  • 0 in reply to Conor
    TI__Guru* 93670 points

    Hi Conor,

    When you set 0x28 = 0x22, there is no need to rewrite.

    Regards, Nasser