SN65DSI83-Q1: No output on LVDS Display

As this is a sporadic issue, and then the issue arises there is a PLL unlock this is most likely due to jitter on the input clock. Are you using DSI clock or REF clock as your LVDS clock source?

Hello Vishesh,

Thank you for your response!t

We are utilizing the DSI clock (approx. 200MHz) as our LVDS clock source.

On all operational setups, register 0xE5 holds a value of 0x01. Writing 0xFF to 0xE5 changes this to 0x00.

However, on non-operational setups, register 0xE5 shows values of either 0x0D or 0x09 initially. Writing 0xFF to 0xE5 changes these to 0x0C or 0x08 respectively.

Our setup involves an Android-based SoC where the SN65DSI83-Q1 related I2C register configuration is handled within the bootloader itself.

Below attached are the display parameters. 

Regards,

Avish Jain

Hey Avish, 

Is there a possibility to use a REF clock rather than the DSI clock? A REF clock will provide a cleaner clock which will be easier to latch onto.

Additionally, are you meeting the power on timings?

Hi, Vishesh,

Currently we don't have provision to provide REFCLK to the SN65DSI83 in the Board. Do we have any other solution/suggestion?

Thanks,

Balaji V

Have you tried boosting the EQ of the DSI83-Q1?

Hi Vishesh,

1. Please find attached the Initialization sequence waveform.

2. We attempted to boost the EQ (0xCC to 0x10, then SOFT_RESET), but unfortunately, it did not work.

3. Upon manually reading back the registers (via i2cget), we noticed that all values are as configured.

The DSI waveforms look incorrect. Can you confirm the DSI timings with the waveform as seen in step 4 in this document?

Link: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85?tisearch=e2e-sitesearch&keymatch=sn65dsi84#

It seems you are configuring the device correctly, and the initialization sequence look ok. However, the DSI clock looks very noisy and the data looks incorrect. If you have a protocol analyzer, please confirm the waveforms of each.

Avish Jain said:

We are encountering a random issue in few of our custom hardware boards, where their is no output on the LVDS Display.

Is this what the DSI waveforms look like in the functional and non-functional boards?

Hello Vishesh, 

1. Please find attached the initialization sequence waveform from a functional board. 

Reference Debug Guide: (16) [FAQ] SN65DSI84: No display output with SN65DSI83, SN65DSI84, SN65DSI85 - Interface forum - Interface - TI E2E support forums

Here is the tuner tool:

 4135.DSI Tuner 2.1.zip

Thanks Vishesh for providing the Reference Debug Guide and the DSI Tuner tool. We will review them and get back to you shortly.

As discussed, I am attaching the initialization sequence waveform from a non-functional board (This waveform was recorded using the same measurement setup as that used for the functional board)

Hey Avish,

It seems the initialization is ok as the color bar works for all displays, and the timing for the initialization is the same across all boards. 

Let me know if you have any issues using the tools provided.

Additionally, are you able to do an ABA swap of the nonfunctional chip to see if the issue follows the chip?

Best,

Vishesh Pithadiya

Avish

For the Initialization sequence waveform, what signals are captured with Channel 1, 2, 3, and 4?

Thanks

David

Hello David, 

Channel 1 - EN pin (Not present in the last two white DSO images)

Channel 2 - I2C SCL

Channel 3 - DA0P (MIPI Data)

Channel 4 - DACP (MIPI CLK)

Also, we are not able to install the DSI Tuner software - 

Avish

For the installation of DSI Tuner SW, please see attached Java installer. 

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/jre_2D00_6u23_2D00_windows_2D00_i586_2D00_s.exe

Looking at the scope waveform, since you are using a DSI clock as the clock source, you need to make sure you have a valid DSI clock before the DSI83-Q1 EN pin goes from low to high. If you can provide a valid DSI clock before EN goes from low to high, are you able to see the PLL locking?

Thanks

David

Hello David, 

1. We have successfully installed the DSI Tuner software, thanks for your assistance.
2. We are providing a valid DSI clock before transitioning EN from low to high. This is confirmed by the attached waveform, though please note the noise is due to the measurement setup. We have also included waveforms from the same hardware board using a different measurement setup, which had only three functional probes.
   
   
   
3. We performed ABA swaps on two non-functional boards -
   1. On one board, the display briefly turned on but then remained black.
   2. On the other board, the display functioned for approximately an hour before also going black.
      
      
4. On all non-functional boards, we are always able to generate a pattern (Reg 0x3C -> 0x10)

Also, can you please help verify our register settings. I'm attaching the display specifications for the reference. 

Avish

Let me check on the register setting and get back to you on it.

But the clock in high speed mode should have a typical 400mVpp amplitude. With probe set to 500mV per division, we should see a clock signal with bigger amplitude, are we sure the MIPI source is driving the DSI clock? If it is, is it possible to increase the clock amplitude? The DSI83-Q1 HS differential input voltage is minimum of 100mV, I want to make sure the clock amplitude is above the minimum input requirement.

Thanks

David

Avish

I checked the register setting using the DSI Tuner SW and it looks ok.

Thanks

David

Hey Avish,

Any update?

Hello Vishesh/David, 

We are badly stuck with this issue.

A. DSI Tuner

1. We used DSI Tuner with below settings to generate CSR List. 
   
   
   
   
   
2. Below is the CSR List exported from the DSI Tuner. 
   
   0x09 0x00
   0x0A 0x05
   0x0B 0x10
   0x0D 0x00
   0x10 0x26
   0x11 0x00
   0x12 0x27
   0x13 0x00
   0x18 0x78
   0x19 0x00
   0x1A 0x03 [We set 0x1A to 0x01, as we have 100Ohm differential termination]
   0x1B 0x00
   0x20 0x00
   0x21 0x05
   0x22 0x00
   0x23 0x00
   0x24 0x00
   0x25 0x00
   0x26 0x00
   0x27 0x00
   0x28 0x21
   0x29 0x00
   0x2A 0x00
   0x2B 0x00
   0x2C 0x0c
   0x2D 0x00
   0x2E 0x00
   0x2F 0x00
   0x30 0x03
   0x31 0x00
   0x32 0x00
   0x33 0x00
   0x34 0x10
   0x35 0x00
   0x36 0x00
   0x37 0x00
   0x38 0x00
   0x39 0x00
   0x3A 0x00
   0x3B 0x00
   0x3C 0x00
   0x3D 0x00
   0x3E 0x00
   
   
3. Could you please verify the settings entered in the DSI Tuner Utility w.r.t our Panel specifications (uploaded in one of the previous comments).
   
   
4. We tried these CSR settings on one non-functional board, the display is still black. 0xE5 reg shows 0x08.

B. DSI CLOCK

1. We are able to generate test pattern on every non-functional board. When pattern is generated, 0xE5 reg shows 0x00.
   
   
2. Do you still think, MIPI DSI Clock has issues?
   

C. DSI DATA

1. In one of the previous comments, you mentioned that DSI Data looks incorrect.
   
   
2. Right now, we do not have a high speed DSO or differential probe or protocol analyser. 
   
   
3. Do you have any suggestion on this? Could you please explain more on why this data looks incorrect?

Regards,

Avish

Hello David, 

Please review the MIPI DSI Waveforms, now captured with a proper measurement setup. 

HERO_SBDT_MIPI_DSI_Timing_Measurement_14_08_2024.pdf

cc: Balaji Vayavur

Regards, 

Avish Jain