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TCAN4550: What is the minimum frequency clock required to run the CAN bus at 125Kbps?

Sandra Capri
Prodigy 20 points
Part Number: TCAN4550


Tool/software:

In section 9.1.1 of the TI manual for the TCAN4550, it says:

Selecting the crystal or clock input depends upon system implementation. To support 2 and 5 Mbps CAN FD the clock in or crystal needs to have 0.5% frequency accuracy. The minimum value of 20 MHz is needed to support CAN FD with a rate of 2 Mbps.  The recommended value for CLKIN or crystal is 40 MHz to meet CAN FD rates up to 5 Mbps data rates in order to support higher data throughout

We are planning on running our CAN bus no faster than 125Kbps.  Can you tell me what the minimum clock frequency needs to be for running the bus at that speed (we are assuming it would be less than a 20MHz clock because we see the scaling down from 40MHz to 20MHz when dropping from 5Mbps to 2Mbps)?

Additionally, can you tell me the required frequency accuracy to support running at a rate of 125Kbps?

Thank you!

Sandra Capri

  • 0
    TI__Mastermind 33780 points

    Hello Sandra,

    The standard defines the total number of time quanta in a nominal bit time shall be programmable at least from 8 to 25 for implementations that are not FD enabled. For implementations that are FD enabled, the total number of time quanta in a data bit time shall be programmable at least from 5 to 25 and in a nominal bit time at least from 8 to 80.

    So technically speaking you need 8 time quanta per CAN bit which means that the OSC clock frequency would need to be 8x the CAN frequency.  Therefore a 125k CAN frequency would require a minimum OSC clock frequency of 1MHz. 

    The TCAN4550 was designed to use either a 20MHz or 40MHz crystal which are standard values for CAN applications.  This clock is not just used to generate the CAN bit timings, but it also is used as a base for other timer related values in the device such as watchdog window as an example.  Using a different frequency is possible, but these other values would need to scale accordingly.

    There is also a dependency that the OSC clock frequency needs to be at least 2MHz greater than the SPI clock frequency in order for the FIFO that handles the SPI clock to OSC clock domain crossing to function properly and not create SPI errors.  Using a low OSC clock frequency will restrict the maximum SPI frequency as well.

    The minimum recommended clock frequency for the TCAN4550 is 20MHz.  If you chose to use a lower clock frequency, then you will need to scale the SPI frequency and other timing values accordingly.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    Prodigy 20 points

    Hello Jonathan,

    Thank you for your informative response!  We are considering the implications of the SPI dependency.  Because it appears that it takes around 16 SPI transactions to send and receive a message over SPI, we increased the SPI speed to 8MHz, and were considering 16MHz for SPI.  But this could cause our required OSC clock frequency to be higher than we desired.

    We're still interested in the answer to the question - in case you missed it:

    • Additionally, can you tell me the required frequency accuracy to support running at a rate of 125Kbps?

    Thank you!

    Sandra

  • 0 in reply to Sandra Capri
    TI__Mastermind 33780 points

    Hello Sandra,

    To support 16MHz SPI, you will need a minimum OSC clock frequency of 18MHz because the OSC frequency must be at least 2MHz greater than the SPI clock frequency.

    Regarding your question on accuracy, the ISO 11898-1:2015 standard defines the "tolerance range for oscillator frequencies" in section 11.3.2.5.  The tolerance of a node clock oscillator frequency (fosc) around the nominal frequency (fnom) shall be given by the range [(1 - df) x fnom ≤ fosc ≤ (1 + df) x fnom].  The tolerance (df) depends on the length of the time quantum, the segments of the bit time, and on the synchronization jump width.  The maximum  difference between the node clock oscillators of any two nodes shall be 2 x df x fnom.

    The maximum tolerance df of fosc chall meet the following conditions:

    The conditions in formulas (3) and (4) shall be met for Classical Frames; all conditions of formulas (3) to (7) shall be met for FD frames.

    It is to be considered that SJW may not be larger than the smaller of the phase buffer segments and that the propagation time segment limits that part of the bit time that may be used for the phase buffer segments.

    Generally speaking you have higher tolerance with a faster clock frequency that allows more time quantum to be used for the bit period.  This reduces the error in the sample point within the bit period.

    Regards,

    Jonathan