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DP83822IF: Application Inquries

Kazuki Itoh
Genius 10730 points
Part Number: DP83822IF

Tool/software:

Hi team,

Could you please help to answer inqueries below?

  1. Could you let me know the maximum value of the T5 Fast Link Pulse transmission delay post power up on 7.6 Timing Requirements, Power-Up Timing?
  2. Regarding MDIO I/F, is it allowed to stop providing the clock if MDIO access is not used?
  3. If MDC clock is stopped and then accecc by MDIO again, is it possible to access that if the MDC clock is input?
    Also, please let me know if any limitation from MDC clock input to MDIO access.
  4.  In the table 0x0025 MLEDCRのBIT[1:0] > MLED Route to LED_0, the default is described as 0b00=MLED routed to COL.
    Isn't it 0b11=MLED routed to LED_0?
  5. In tha table 8-46.0x003E PTPPSEL BIT[6:4],[2:0], the default is shown as 0b000. However, it is not shown as 0b000 on the FUNCTION.
    Is it okay to leave it as 0b000 when IEEE1588 is not used?
  6.  In the table 8-48.0x0040 Fiber Far-End Fault Generation/Detection Force, my customer doesn't get what this is.
    Could you let me know the datahseet page which explain this functionality?
  7. Table 8-49.0x0042 TXCPSR is only needed when using MII and it is not needed for RGMII, correct?
  8. Regarding Table 8-51.0x0106 DFCR1, should it be modified when short cable is used? Or, is it okay to leave it default?
  9. Regarding Table 8-64.0x0170 CDSCR, is it okay to leave it as default when the TDR is not used?
  10. Regarding Table 8-66.0x0173 CDSCT3, is it needed to modify when the long cable is used?
  11. Regarding Table 8-67.0x0177 CDSCT4, is it needed to modify when the short cable is used?
  12. Regarding Table 8-91.0x0456 GENCFG BIT[3], it is mentioned as Note:IPGs <200ns should only be used when operating with a MII MAC IF configuration.”
    Does this mean Min IPG Enable should be set from 0b1 to 0b0 if the I/F except for MII is used?
  13. In Table 8-94.0x0462 IOCTRL1 BIT[10:8]RX_D3/GPIO_3Control FUNCTION, it is shown as 0b000:Normal operation.
    Does normal operation operate in RX_D3?
  14. In Table 8-94.0x0462 IOCTRL1 BIT[10:8]RX_D3/GPIO_3Control FUNCTION, it is shown as 0b000:Normal operation.
    Does normal operation operate in COL?
  15. In 9.2.2.2.4 MDI Layout Guidelines, there's description regarding RJ45 connection. Could you provide the guideline fro 100BASE-FX application as well?
  16. What is the recommended spec of the AVD supply ferrite bead on Figure 9-2?
  17. What is the recommended spec o VDDIO/AVD ferrite bead on Figure 10-1?
  18. Could you let me know the maximum current and power comsumptions on Table 10-1?
    Also, which pin sonsumes the current specified on MAGNETIC SUPPLY in Table 10-1?

Best regards,

Kazuki Itoh

  • 0
    TI__Mastermind 24988 points

    Hi Itoh-san,

    Please allow me some time to review these queries and get back to you.

    I should have feedback by 7-22.

    Thank you,

    Evan

  • +1 in reply to Evan Mayhew
    TI__Mastermind 24988 points

    Hi Itoh-san,

    Please see my feedback below:

    1) T5(max) is not available to share.

    2) Yes, it is okay if MDC is inactive while register access is not being used.

    3) As long as timing requirements in Table 7.9 are met, register reads/writes via MDIO/MDC can be performed. MDC can stop/start as needed before MDIO transaction occurs. Please let me know if this answers your question.

    4) Default value is 0x25[1:0] = '00', routing to COL. This can be written to '11' to instead route to LED_0.

    5) Yes, default value of 0x3E[6:4, 2:0] is okay if IEEE1588 is not being used.

    6) Description of this feature is not currently included in datasheet, I have noted to add this in next revision. Please refer to this article for description of FEF functionality:

    https://community.fs.com/article/understand-lfp-and-fef-of-media-converter.html

    7) That is correct.

    I am looking to give feedback on remaining questions later today, I appreciate your patience.

    Thank you,

    Evan

  • +1 in reply to Evan Mayhew
    TI__Mastermind 24988 points

    Continuing feedback below:

    8) It is okay to leave at default. If the customer faces issues with shorter cables, we can look to debug then.

    9) Okay to leave at default.

    10,11) Okay to leave at default if TDR is not used. These can be tuned if using TDR for long/short cable cases.

    12) I will check this and get back to you.

    13) Normal operation acts as RX_D3

    14) I assume you are instead referring to 0x463[2:0]. For 0x463[2:0] = '000' (Normal Operation), COL / GPIO_2 acts as COL.

    15) Under 9.2.2.2.4, points 1/2 apply to layout for Fiber as well. For further guidance, please refer to DP83822EVM schematic and layout files.

    16,17) I will check.

    18) Please consider "MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets, 125C" as the use-case with maximum power/current draw. The remaining cases were measured at nominal 25C, and will vary power/current with temperature.

    MAGNETIC SUPPLY is the current draw for only the magnetics, from the rail used to connect the center taps. AVD is the current draw measured relative to AVD pin of PHY.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    TI__Genius 10730 points

    Hi Evan-san,

    Thank you for the answers.

    Please answer questions 12, 16, and 17 as well.

    Also I have a couple of additional questions.

    1. T5 is the time from hardware RESET_N asserts to high. So if the power-down is disabled by INT/PWN pin, the LFP is output instantaneously, correct?

    4. You mentioned default value is 0x25[1:0] = '00', routing to COL. Is default MLED assigned to COL pin?

    6. In order to disable FEF, how shoud 0x0040 on Table 8-48 be configured?

    Best regards,

    Kazuki Itoh

  • +1 in reply to Kazuki Itoh
    TI__Mastermind 24988 points

    Hi Itoh-san,

    1) Can you help me understand how power-down disable is related to FLP delay during RESET_N? From when RESET_N is first driven low, minimum T1+T5 time will pass before FLP burst is output.

    4) MLED is assigned to COL by default.

    6) 0x40[6:5] = '11' to disable FEF generation/detection.

    I will share 12/16/17 feedback today.

    Thank you,

    Evan

  • +1 in reply to Evan Mayhew
    TI__Mastermind 24988 points

    Continuing feedback:

    16/17) Please follow spec similar to BLM21BD121SN1D. We have not validated a variety of ferrite beads, but have seen that this model helps filter noise when used.

    12) Waiting for feedback from team, sorry for the delay here.

    Thank you,

    Evan

  • +1 in reply to Evan Mayhew
    TI__Mastermind 24988 points

    Hi Itoh-san,

    12) We have not seen any issues with default value of 0x456 for non-MII MAC interfaces. This setting is acceptable for RMII/RGMII communication.

    Thank you,

    Evan