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Original question:

DS280DF810: PRBS generator

DS280DF810: There is a packet error issue with the exchange interface when using the ds250df810 receiver

? ??
Prodigy 10 points
Part Number: DS280DF810
Other Parts Discussed in Thread: DS250DF810, , DS250DF410

Tool/software:

The switching chip is on the motherboard, and two daughter cards are connected to the motherboard from the panel. The QSFP28 100G port on the daughter card is connected to the 100G port of the switching chip on the motherboard through the DS250DF810.

From the QSFP28 direction of the optical module to the receiving port of the switch chip, some switch chip ports show an increase in FCS error packets that cannot be eliminated; Some interfaces are stable without FCS error packets.

Select the corresponding channel of ds250df810 chip with FCS error packet and without FSC error packet, and its configuration is shown in the attachment;

Are there any other parameters that can be adjusted and optimized？

Thanks

odp1200-Right-Port3Z10-withFCSerror.logodp1200-Right-Port0Z10-NO-FCSerror.log

  • 0
    Prodigy 10 points

    The distance between QSFP28 optical module and DS250df810 is only 2-3 inches, with a maximum attenuation of about 3db

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    I'm working on reviewing your logs and will have more feedback tomorrow.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    To improve the reception status on the ingress side:
    1. To adapt to the optimal CTLE parameters, choose Rx Adapt Mode 2
    2. It has been observed that setting CTLE boost can achieve good anti-interference ability, and registers 0x2d and 0x3 have been set.
    3. To adapt to the impact of temperature changes on DFE, 0x7F and 0x7d are set to be adaptive;
    Under this configuration, 0x3d 0x8e, 0x3e 0x40, 0x3f 0x40; Modify the DFE parameters and see that the 0x3d register is configured to 0x9f. A better eye diagram can be seen on the RX interface of the switch chip. Alternatively, set 0x3e to 0x45 or 0x3f to 0x42;
    Our panel has multiple 100G ports and uses multiple DS250DF810,
    1. Are there any other improvement measures based on the parameters?, Or other methods to help me find the optimal parameters for each buffer channel?
    2. Is there any optimization in the input section? Used to adapt different optical modules and confirm our parameters;
    3. Are there any conditions for generating prbs31 when using prbs? After CDR locking, I tried to enable the PRBS transmission of DS250df810, but the receiving interface of the switch chip on the other end was not recognized. Do I need any other conditi

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Apologies for the delay.

    I noticed in your register dump that you're manually setting CTLE boost.  For a low insertion loss channel, it's possible that the signal is getting over-equalized.  I'd consider trying CTLE boost value 0 if you haven't already.

    Additionally, we have an alternative CTLE boost table and FOM setting that can help improve adaptation in some cases.  Please accept my friend request on E2E and I can share these with you over private message.

    To improve the reception status on the ingress side:

    1. To adapt to the optimal CTLE parameters, choose Rx Adapt Mode 2
      • Adapt mode 2 generally provides optimal equalization since it enables DFE.  For very low insertion loss cases, manually setting CTLE may help performance.
    2. It has been observed that setting CTLE boost can achieve good anti-interference ability, and registers 0x2d and 0x3 have been set.
      • Yes, I think this makes sense for 2-3 dB insertion loss.
    3. To adapt to the impact of temperature changes on DFE, 0x7F and 0x7d are set to be adaptive;
      • Good, this is the recommended change for temperature compensation.
    4. Under this configuration, 0x3d 0x8e, 0x3e 0x40, 0x3f 0x40; Modify the DFE parameters and see that the 0x3d register is configured to 0x9f. A better eye diagram can be seen on the RX interface of the switch chip. Alternatively, set 0x3e to 0x45 or 0x3f to 0x42;
      • The TX FIR settings typically have to be manually tuned, as you've already done.  You'll want to optimize the eye at RX of your switch.  You can also perform TX FIR sweep and measure eye or BER to determine best settings.

    Our panel has multiple 100G ports and uses multiple DS250DF810:

    1. Are there any other improvement measures based on the parameters?, Or other methods to help me find the optimal parameters for each buffer channel?
      • I will send you an alternative CTLE table and FOM to try.
      • We generally observe good BER performance if the retimer eye opening monitor measures HEO/VEO of at least 0.4 UI and 200 mVppd.  In general, I'd recommend targeting eye openings at least this large.
    2. Is there any optimization in the input section? Used to adapt different optical modules and confirm our parameters;
      1. For optical modules, I think manually setting CTLE to a low boost value like 0 is probably fine.  For DAC, you may want to re-enable CTLE adaptation.
    3. Are there any conditions for generating prbs31 when using prbs? After CDR locking, I tried to enable the PRBS transmission of DS250df810, but the receiving interface of the switch chip on the other end was not recognized. Do I need any other condition?
      1. The key requirement for generating PRBS31 is to have CDR lock.  Sometimes I have seen that PRBS patterns are not recognized if there is a polarity inversion in the signal chain.  Is it possible to try inverting the signal from the retimer to see if that helps the switch chip recognize the pattern?  This can be done by changing the polarities of the TX FIR taps.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    please send a alternative CTLE table and FOM to me.

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    The DS250DF810 chip we previously used had a 0xf0 register of 0x31; The batch of chips currently in use, I read that the 0xf0 register is 0x32

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    ? ?? said:
    The DS250DF810 chip we previously used had a 0xf0 register of 0x31; The batch of chips currently in use, I read that the 0xf0 register is 0x32

    DS250DF810 devices may have 0xF0 register value of 0x31 or 0x32.  This is typical behavior.

    I've send the CTLE table and FOM to you via private message.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    May I ask, when adjusting the parameters of DS250DF810, I found that sometimes the 0x78 register changes to 0x20;
    There is a signal displayed, but CDR cannot be locked;
    May I ask which direction this needs to be adjusted in?

    thank

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    What parameters are you adjusting?  You can also read register 0x02 for more details on CDR lock status. 

    CDR Lock has a couple requirements:

    - Data rate must be configured correctly

    - PPM check must be met (generally fine if data rate is configured correctly)

    - HEO/VEO minimum lock criteria must be met.  By default, DS280DF810 will not lock if internal eye HEO/VEO is very low.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    May I ask about the status description of register 0x2?
    We have found that CDR in the 0x78 register has experienced a jump, and we hope to investigate the fault issue on this interface link;

    There is no description of register 0x2 and register 0xc in my document;

    Thanks

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Do you have the programming guide?  This should have descriptions in the register map.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    <DS250DF810_SNLU182_Programmers_Guide_Confidential.pdf>

    I can see that the 0x2 register is CDR_STATUS;

    Bit7 Introduction “this register is used to read the status of internal signal.select waht is observable on this ubs using Reg_0xc"

    But 0xc is reserved

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Can you confirm that you have the latest revision (revision H)?  You can download the latest version from the DS280DF810 secure resources folder on ti.com.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    We have made an optical module similar to QSFP28 using the DS250df410 chip, and we want to use its receiving eye diagram to view our signal transmission situation.
    The current sending path is BFtx ->DS250DF810 rx ->DS250DF810 tx ->DS250DF410 rx
    The receiving path is DS250DF410tx ->DS250DF810 rx ->DS250DF810 tx ->BFrx
    Through measurement, it was found that the receiving eye diagram HEO of the rx sent from BF's switching chip to DS250DF810 is between 0.5-0.7, and VEO is over 300 mv
    When it comes to DS250DF410 rx, the HEO of the receiving eye diagram is generally between 0.3125-0.4, and the VEO is between 185-250mv;

    Is there a good way to improve HEO?
    Is it possible to use bypass mode?
    Or by examining which registers can be used to assist in adjusting parameters?

    Thanks

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    What is the insertion loss from DS280DF810 TX -> DS250DF410 RX?  DS250DF410 has high minimum CTLE boost.  Is it possible that the signal is getting over-equalized?

    Have you tried adjusting TX FIR settings on DS280DF810?

    You can try bypass mode, but you will not be able to measure HEO/VEO on the device configured to bypass mode since HEO/VEO measurements are dependent on CDR lock.  Also, bypass mode will have increased jitter since signal is not being retimed.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    What is the insertion loss from DS280DF810 TX -> DS250DF410 RX?  
    The maximum size here is 3 inches, and according to the assessment, it will not exceed 3dB；

    DS250DF410 has high minimum CTLE boost.  Is it possible that the signal is getting over-equalized?
    We want to use DS250DF410 to test the transmission of this interface, hoping to evaluate the transmission pre emphasis parameters of these interfaces based on the receiving eye diagram and other data of DS250DF410. Can we do this?

    Have you tried adjusting TX FIR settings on DS280DF810?
    Previously, there was a set of parameters that were adapted. Sometimes the interface on the switch chip may cause interface UP DOWN due to remote faults. We want to adjust and optimize the sending of pre emphasis parameters. Can the receiving eye diagram and other parameters of DS250DF410 be used for our detection and verification?
    I am now plugging it into the interfaces of several other devices and have found that some can reach 0.6 and have an eye height of 270mv.
    The interface of this device is sent to DS250df810, some of which have a 0.5 and an eye height of 220mv; I am thinking of adjusting the tx FIR of the DS250DF810. Do I need any other settings for this DS250DF410? (Currently using its default settings, obtaining eye diagram data directly after power on)。
    Thank you.

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Due to high minimum CTLE of DS250DF410, it may not be the best choice for optimizing DS280DF810 TX FIR values for this low insertion loss case.  However, if you don't have any other alternatives, the information you get from DS250DF410 may still be useful.

    I have a couple suggestions of things you could try to improve the eye on DS250DF410.

    1. By default, DS250DF410 uses adapt mode 1.  This involves automatically adapting CTLE.  You can check the CTLE index it has adapted to.  If the index is not 0, then you can try manually setting the CTLE to 0 to see if this improves the eye.
    2. The DS250DF410 also has adapt mode 2.  Adapt mode 2 adapts CTLE and DFE.  DFE may help in low insertion loss cases.  You could try adapt mode 2 to see if this improves the eye on DS250DF410.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    May I ask when the input eye diagram parameters (0x27, 0x28) from the optical module to the ds250df810 can be correctly restored when the ds250df10 is in 10G mode?
    We have observed that the DS250DF810 on site receives signals from the optical module, with 0x78 being 0x30 and 0x2 being 0xd8; But 0x27 is 0x4, 0x28 is 0x24 At this time, the interface cannot be up. It has been up before, but there were many error packets.
    The input and output parameters of the dump interface ds250df10 are shown in the attachment.
    Thank you.

  • 0 in reply to ? ??
    Prodigy 10 points

    8_26_port_3_1_33_dump_buffer.txt 
    输入部分buffer寄存器参数   Input
Mon Aug 26 18:18:14 2024 subcard8 ds250df810 addr:4c channel:5 show shared register:
Mon Aug 26 18:18:14 2024        reg_addr        value
Mon Aug 26 18:18:14 2024        0x0             0x0
Mon Aug 26 18:18:14 2024        0x1             0x30
Mon Aug 26 18:18:14 2024        0x2             0x0
Mon Aug 26 18:18:14 2024        0x3             0x0
Mon Aug 26 18:18:14 2024        0x4             0x9
Mon Aug 26 18:18:14 2024        0x5             0x1
Mon Aug 26 18:18:14 2024        0x6             0x0
Mon Aug 26 18:18:14 2024        0x7             0x0
Mon Aug 26 18:18:14 2024        0x8             0x0
Mon Aug 26 18:18:14 2024        0x9             0x0
Mon Aug 26 18:18:14 2024        0xa             0x0
Mon Aug 26 18:18:14 2024        0xb             0x40
Mon Aug 26 18:18:14 2024        0xc             0x0
Mon Aug 26 18:18:14 2024        0xd             0x50
Mon Aug 26 18:18:14 2024        0xe             0x1
Mon Aug 26 18:18:14 2024        0xf             0x0
Mon Aug 26 18:18:14 2024        0x10            0xff
Mon Aug 26 18:18:14 2024        0x11            0x0
Mon Aug 26 18:18:14 2024        0x12            0x91
Mon Aug 26 18:18:14 2024 ---------------------------------------------
Mon Aug 26 18:18:14 2024 ---------------------------------------------
Mon Aug 26 18:18:14 2024 subcard8 ds250df810 addr:4c channel:5 show register:
Mon Aug 26 18:18:14 2024        reg_addr        value
Mon Aug 26 18:18:14 2024        0x0             0x0
Mon Aug 26 18:18:14 2024        0x1             0x80
Mon Aug 26 18:18:14 2024        0x2             0xd8
Mon Aug 26 18:18:14 2024        0x3             0x0
Mon Aug 26 18:18:14 2024        0x4             0x1
Mon Aug 26 18:18:14 2024        0x5             0x1
Mon Aug 26 18:18:14 2024        0x6             0x1
Mon Aug 26 18:18:14 2024        0x7             0x1
Mon Aug 26 18:18:14 2024        0x8             0x73
Mon Aug 26 18:18:14 2024        0x9             0x0
Mon Aug 26 18:18:14 2024        0xa             0x0
Mon Aug 26 18:18:14 2024        0xb             0x63
Mon Aug 26 18:18:14 2024        0xc             0x0
Mon Aug 26 18:18:14 2024        0xd             0x80
Mon Aug 26 18:18:14 2024        0xe             0x93
Mon Aug 26 18:18:14 2024        0xf             0x69
Mon Aug 26 18:18:14 2024        0x10            0x0
Mon Aug 26 18:18:14 2024        0x11            0x20
Mon Aug 26 18:18:14 2024        0x12            0x83
Mon Aug 26 18:18:14 2024        0x13            0xb0
Mon Aug 26 18:18:14 2024        0x14            0x4
Mon Aug 26 18:18:14 2024        0x15            0x10
Mon Aug 26 18:18:14 2024        0x16            0x7a
Mon Aug 26 18:18:14 2024        0x17            0x36
Mon Aug 26 18:18:14 2024        0x18            0x40
Mon Aug 26 18:18:14 2024        0x19            0x20
Mon Aug 26 18:18:14 2024        0x1a            0x58
Mon Aug 26 18:18:14 2024        0x1b            0x3
Mon Aug 26 18:18:14 2024        0x1c            0x90
Mon Aug 26 18:18:14 2024        0x1d            0x0
Mon Aug 26 18:18:14 2024        0x1e            0x3
Mon Aug 26 18:18:14 2024        0x1f            0xb
Mon Aug 26 18:18:14 2024        0x20            0x0
Mon Aug 26 18:18:14 2024        0x21            0x0
Mon Aug 26 18:18:14 2024        0x22            0x0
Mon Aug 26 18:18:14 2024        0x23            0x40
Mon Aug 26 18:18:14 2024        0x24            0x0
Mon Aug 26 18:18:15 2024        0x25            0x0
Mon Aug 26 18:18:15 2024        0x26            0x0
Mon Aug 26 18:18:15 2024        0x27            0x4
Mon Aug 26 18:18:15 2024        0x28            0x24
Mon Aug 26 18:18:15 2024        0x29            0x40
Mon Aug 26 18:18:15 2024        0x2a            0x5a
Mon Aug 26 18:18:15 2024        0x2b            0xa
Mon Aug 26 18:18:15 2024        0x2c            0xf6
Mon Aug 26 18:18:15 2024        0x2d            0x30
Mon Aug 26 18:18:15 2024        0x2e            0x0
Mon Aug 26 18:18:15 2024        0x2f            0x4
Mon Aug 26 18:18:15 2024        0x30            0x0
Mon Aug 26 18:18:15 2024        0x31            0x40
Mon Aug 26 18:18:15 2024        0x32            0x11
Mon Aug 26 18:18:15 2024        0x33            0x88
Mon Aug 26 18:18:15 2024        0x34            0xbf
Mon Aug 26 18:18:15 2024        0x35            0xf
Mon Aug 26 18:18:15 2024        0x36            0x30
Mon Aug 26 18:18:15 2024        0x37            0x0
Mon Aug 26 18:18:15 2024        0x38            0x10
Mon Aug 26 18:18:15 2024        0x39            0x60
Mon Aug 26 18:18:15 2024        0x3a            0x0
Mon Aug 26 18:18:15 2024        0x3b            0x33
Mon Aug 26 18:18:15 2024        0x3c            0x8e
Mon Aug 26 18:18:15 2024        0x3d            0x82
Mon Aug 26 18:18:15 2024        0x3e            0x41
Mon Aug 26 18:18:15 2024        0x3f            0x1
Mon Aug 26 18:18:15 2024        0x40            0x0
Mon Aug 26 18:18:15 2024        0x41            0x40
Mon Aug 26 18:18:15 2024        0x42            0x50
Mon Aug 26 18:18:15 2024        0x43            0x80
Mon Aug 26 18:18:15 2024        0x44            0x90
Mon Aug 26 18:18:15 2024        0x45            0xc0
Mon Aug 26 18:18:15 2024        0x46            0xd0
Mon Aug 26 18:18:15 2024        0x47            0xd1
Mon Aug 26 18:18:15 2024        0x48            0xd5
Mon Aug 26 18:18:15 2024        0x49            0xd8
Mon Aug 26 18:18:15 2024        0x4a            0xea
Mon Aug 26 18:18:15 2024        0x4b            0xf7
Mon Aug 26 18:18:15 2024        0x4c            0xfd
Mon Aug 26 18:18:15 2024        0x4d            0xee
Mon Aug 26 18:18:15 2024        0x4e            0xef
Mon Aug 26 18:18:15 2024        0x4f            0xff
Mon Aug 26 18:18:15 2024        0x50            0x0
Mon Aug 26 18:18:15 2024        0x51            0x0
Mon Aug 26 18:18:15 2024        0x52            0x0
Mon Aug 26 18:18:15 2024        0x53            0x0
Mon Aug 26 18:18:15 2024        0x54            0x0
Mon Aug 26 18:18:15 2024        0x55            0x0
Mon Aug 26 18:18:15 2024        0x56            0x0
Mon Aug 26 18:18:15 2024        0x57            0x0
Mon Aug 26 18:18:15 2024        0x58            0x0
Mon Aug 26 18:18:15 2024        0x59            0x0
Mon Aug 26 18:18:15 2024        0x5a            0x0
Mon Aug 26 18:18:16 2024        0x5b            0x0
Mon Aug 26 18:18:16 2024        0x5c            0x0
Mon Aug 26 18:18:16 2024        0x5d            0x0
Mon Aug 26 18:18:16 2024        0x5e            0x0
Mon Aug 26 18:18:16 2024        0x5f            0x0
Mon Aug 26 18:18:16 2024        0x60            0x0
Mon Aug 26 18:18:16 2024        0x61            0x0
Mon Aug 26 18:18:16 2024        0x62            0x0
Mon Aug 26 18:18:16 2024        0x63            0x0
Mon Aug 26 18:18:16 2024        0x64            0x0
Mon Aug 26 18:18:16 2024        0x65            0x0
Mon Aug 26 18:18:16 2024        0x66            0x0
Mon Aug 26 18:18:16 2024        0x67            0x20
Mon Aug 26 18:18:16 2024        0x68            0x0
Mon Aug 26 18:18:16 2024        0x69            0xa
Mon Aug 26 18:18:16 2024        0x6a            0x21
Mon Aug 26 18:18:16 2024        0x6b            0x40
Mon Aug 26 18:18:16 2024        0x6c            0x0
Mon Aug 26 18:18:16 2024        0x6d            0x0
Mon Aug 26 18:18:16 2024        0x6e            0x0
Mon Aug 26 18:18:16 2024        0x6f            0x0
Mon Aug 26 18:18:16 2024        0x70            0x5
Mon Aug 26 18:18:16 2024        0x71            0x23
Mon Aug 26 18:18:16 2024        0x72            0x0
Mon Aug 26 18:18:16 2024        0x73            0x0
Mon Aug 26 18:18:16 2024        0x74            0x0
Mon Aug 26 18:18:16 2024        0x75            0x0
Mon Aug 26 18:18:16 2024        0x76            0x21
Mon Aug 26 18:18:16 2024        0x77            0x1a
Mon Aug 26 18:18:16 2024        0x78            0x30
Mon Aug 26 18:18:16 2024        0x79            0x10
Mon Aug 26 18:18:16 2024        0x7a            0x0
Mon Aug 26 18:18:16 2024        0x7b            0x0
Mon Aug 26 18:18:16 2024        0x7c            0x0
Mon Aug 26 18:18:16 2024        0x7d            0x48
Mon Aug 26 18:18:16 2024        0x7e            0x13
Mon Aug 26 18:18:16 2024        0x7f            0x2a
Mon Aug 26 18:18:16 2024        0x80            0x1d
Mon Aug 26 18:18:16 2024        0x81            0xe5
Mon Aug 26 18:18:16 2024        0x82            0x0
Mon Aug 26 18:18:16 2024        0x83            0x3
Mon Aug 26 18:18:16 2024        0x84            0x34
Mon Aug 26 18:18:16 2024        0x85            0x0
Mon Aug 26 18:18:16 2024        0x86            0x0
Mon Aug 26 18:18:16 2024        0x87            0x0
Mon Aug 26 18:18:16 2024        0x88            0x0
Mon Aug 26 18:18:16 2024        0x89            0x0
Mon Aug 26 18:18:16 2024        0x8a            0x0
Mon Aug 26 18:18:16 2024        0x8b            0x0
Mon Aug 26 18:18:16 2024        0x8c            0x0
Mon Aug 26 18:18:16 2024        0x8d            0x0
Mon Aug 26 18:18:16 2024        0x8e            0x0
Mon Aug 26 18:18:16 2024        0x8f            0x0
Mon Aug 26 18:18:16 2024        0x90            0x0
Mon Aug 26 18:18:16 2024        0x91            0x0
Mon Aug 26 18:18:17 2024        0x92            0x0
Mon Aug 26 18:18:17 2024        0x93            0x0
Mon Aug 26 18:18:17 2024        0x94            0x0
Mon Aug 26 18:18:17 2024        0x95            0x0
Mon Aug 26 18:18:17 2024        0x96            0x8
Mon Aug 26 18:18:17 2024        0x97            0xff
Mon Aug 26 18:18:17 2024        0x98            0x0
Mon Aug 26 18:18:17 2024        0x99            0x3f
Mon Aug 26 18:18:17 2024        0x9a            0x3f
Mon Aug 26 18:18:17 2024        0x9b            0xe0
Mon Aug 26 18:18:17 2024        0x9c            0x24
Mon Aug 26 18:18:17 2024        0x9d            0xa5
Mon Aug 26 18:18:17 2024        0x9e            0x48
Mon Aug 26 18:18:17 2024        0x9f            0x0
Mon Aug 26 18:18:17 2024        0xa0            0x0
Mon Aug 26 18:18:17 2024        0xa1            0x40
Mon Aug 26 18:18:17 2024        0xa2            0x50
Mon Aug 26 18:18:17 2024        0xa3            0x80
Mon Aug 26 18:18:17 2024        0xa4            0x90
Mon Aug 26 18:18:17 2024        0xa5            0x20
Mon Aug 26 18:18:17 2024        0xa6            0x43
Mon Aug 26 18:18:17 2024        0xa7            0x4
Mon Aug 26 18:18:17 2024        0xa8            0x0
Mon Aug 26 18:18:17 2024 ---------------------------------------------


输出buffer寄存器参数   Output
Mon Aug 26 18:18:24 2024 ---------------------------------------------
Mon Aug 26 18:18:24 2024 subcard8 ds250df810 addr:46 channel:4 show shared register:
Mon Aug 26 18:18:24 2024        reg_addr        value
Mon Aug 26 18:18:24 2024        0x0             0x0
Mon Aug 26 18:18:24 2024        0x1             0x30
Mon Aug 26 18:18:24 2024        0x2             0x0
Mon Aug 26 18:18:24 2024        0x3             0x0
Mon Aug 26 18:18:24 2024        0x4             0x9
Mon Aug 26 18:18:24 2024        0x5             0x1
Mon Aug 26 18:18:24 2024        0x6             0x0
Mon Aug 26 18:18:24 2024        0x7             0x0
Mon Aug 26 18:18:24 2024        0x8             0x0
Mon Aug 26 18:18:24 2024        0x9             0x0
Mon Aug 26 18:18:24 2024        0xa             0x0
Mon Aug 26 18:18:24 2024        0xb             0x40
Mon Aug 26 18:18:24 2024        0xc             0x0
Mon Aug 26 18:18:24 2024        0xd             0x0
Mon Aug 26 18:18:24 2024        0xe             0x0
Mon Aug 26 18:18:24 2024        0xf             0x0
Mon Aug 26 18:18:24 2024        0x10            0xff
Mon Aug 26 18:18:24 2024        0x11            0x0
Mon Aug 26 18:18:24 2024        0x12            0x91
Mon Aug 26 18:18:24 2024 ---------------------------------------------
Mon Aug 26 18:18:24 2024 ---------------------------------------------
Mon Aug 26 18:18:24 2024 subcard8 ds250df810 addr:46 channel:4 show register:
Mon Aug 26 18:18:24 2024        reg_addr        value
Mon Aug 26 18:18:24 2024        0x0             0x0
Mon Aug 26 18:18:24 2024        0x1             0x80
Mon Aug 26 18:18:24 2024        0x2             0xd8
Mon Aug 26 18:18:24 2024        0x3             0x0
Mon Aug 26 18:18:24 2024        0x4             0x1
Mon Aug 26 18:18:24 2024        0x5             0x1
Mon Aug 26 18:18:24 2024        0x6             0x1
Mon Aug 26 18:18:24 2024        0x7             0x1
Mon Aug 26 18:18:24 2024        0x8             0x73
Mon Aug 26 18:18:24 2024        0x9             0x0
Mon Aug 26 18:18:24 2024        0xa             0x0
Mon Aug 26 18:18:24 2024        0xb             0x63
Mon Aug 26 18:18:24 2024        0xc             0x0
Mon Aug 26 18:18:24 2024        0xd             0x80
Mon Aug 26 18:18:24 2024        0xe             0x93
Mon Aug 26 18:18:24 2024        0xf             0x69
Mon Aug 26 18:18:24 2024        0x10            0x0
Mon Aug 26 18:18:24 2024        0x11            0x20
Mon Aug 26 18:18:24 2024        0x12            0x83
Mon Aug 26 18:18:24 2024        0x13            0xb0
Mon Aug 26 18:18:24 2024        0x14            0x4
Mon Aug 26 18:18:25 2024        0x15            0x10
Mon Aug 26 18:18:25 2024        0x16            0x7a
Mon Aug 26 18:18:25 2024        0x17            0x36
Mon Aug 26 18:18:25 2024        0x18            0x40
Mon Aug 26 18:18:25 2024        0x19            0x20
Mon Aug 26 18:18:25 2024        0x1a            0x58
Mon Aug 26 18:18:25 2024        0x1b            0x3
Mon Aug 26 18:18:25 2024        0x1c            0x90
Mon Aug 26 18:18:25 2024        0x1d            0x0
Mon Aug 26 18:18:25 2024        0x1e            0xe9
Mon Aug 26 18:18:25 2024        0x1f            0xb
Mon Aug 26 18:18:25 2024        0x20            0x0
Mon Aug 26 18:18:25 2024        0x21            0x0
Mon Aug 26 18:18:25 2024        0x22            0x0
Mon Aug 26 18:18:25 2024        0x23            0x40
Mon Aug 26 18:18:25 2024        0x24            0x3
Mon Aug 26 18:18:25 2024        0x25            0x0
Mon Aug 26 18:18:25 2024        0x26            0x0
Mon Aug 26 18:18:25 2024        0x27            0x1d
Mon Aug 26 18:18:25 2024        0x28            0xbc
Mon Aug 26 18:18:25 2024        0x29            0x60
Mon Aug 26 18:18:25 2024        0x2a            0x5a
Mon Aug 26 18:18:25 2024        0x2b            0xa
Mon Aug 26 18:18:25 2024        0x2c            0xf6
Mon Aug 26 18:18:25 2024        0x2d            0x30
Mon Aug 26 18:18:25 2024        0x2e            0x0
Mon Aug 26 18:18:25 2024        0x2f            0x4
Mon Aug 26 18:18:25 2024        0x30            0x0
Mon Aug 26 18:18:25 2024        0x31            0x20
Mon Aug 26 18:18:25 2024        0x32            0x11
Mon Aug 26 18:18:25 2024        0x33            0x88
Mon Aug 26 18:18:25 2024        0x34            0xbf
Mon Aug 26 18:18:25 2024        0x35            0xf
Mon Aug 26 18:18:25 2024        0x36            0x30
Mon Aug 26 18:18:25 2024        0x37            0x1
Mon Aug 26 18:18:25 2024        0x38            0x0
Mon Aug 26 18:18:25 2024        0x39            0x60
Mon Aug 26 18:18:25 2024        0x3a            0x0
Mon Aug 26 18:18:25 2024        0x3b            0x33
Mon Aug 26 18:18:25 2024        0x3c            0x8d
Mon Aug 26 18:18:25 2024        0x3d            0x88
Mon Aug 26 18:18:25 2024        0x3e            0x41
Mon Aug 26 18:18:25 2024        0x3f            0x2
Mon Aug 26 18:18:25 2024        0x40            0x0
Mon Aug 26 18:18:25 2024        0x41            0x40
Mon Aug 26 18:18:25 2024        0x42            0x50
Mon Aug 26 18:18:25 2024        0x43            0x80
Mon Aug 26 18:18:25 2024        0x44            0x90
Mon Aug 26 18:18:25 2024        0x45            0xc0
Mon Aug 26 18:18:25 2024        0x46            0xd0
Mon Aug 26 18:18:25 2024        0x47            0xd1
Mon Aug 26 18:18:25 2024        0x48            0xd5
Mon Aug 26 18:18:25 2024        0x49            0xd8
Mon Aug 26 18:18:25 2024        0x4a            0xea
Mon Aug 26 18:18:26 2024        0x4b            0xf7
Mon Aug 26 18:18:26 2024        0x4c            0xfd
Mon Aug 26 18:18:26 2024        0x4d            0xee
Mon Aug 26 18:18:26 2024        0x4e            0xef
Mon Aug 26 18:18:26 2024        0x4f            0xff
Mon Aug 26 18:18:26 2024        0x50            0x0
Mon Aug 26 18:18:26 2024        0x51            0x0
Mon Aug 26 18:18:26 2024        0x52            0x0
Mon Aug 26 18:18:26 2024        0x53            0x0
Mon Aug 26 18:18:26 2024        0x54            0x0
Mon Aug 26 18:18:26 2024        0x55            0x0
Mon Aug 26 18:18:26 2024        0x56            0x0
Mon Aug 26 18:18:26 2024        0x57            0x0
Mon Aug 26 18:18:26 2024        0x58            0x0
Mon Aug 26 18:18:26 2024        0x59            0x0
Mon Aug 26 18:18:26 2024        0x5a            0x0
Mon Aug 26 18:18:26 2024        0x5b            0x0
Mon Aug 26 18:18:26 2024        0x5c            0x0
Mon Aug 26 18:18:26 2024        0x5d            0x0
Mon Aug 26 18:18:26 2024        0x5e            0x0
Mon Aug 26 18:18:26 2024        0x5f            0x0
Mon Aug 26 18:18:26 2024        0x60            0x0
Mon Aug 26 18:18:26 2024        0x61            0x0
Mon Aug 26 18:18:26 2024        0x62            0x0
Mon Aug 26 18:18:26 2024        0x63            0x0
Mon Aug 26 18:18:26 2024        0x64            0x0
Mon Aug 26 18:18:26 2024        0x65            0x0
Mon Aug 26 18:18:26 2024        0x66            0x0
Mon Aug 26 18:18:26 2024        0x67            0x20
Mon Aug 26 18:18:26 2024        0x68            0x0
Mon Aug 26 18:18:26 2024        0x69            0xa
Mon Aug 26 18:18:26 2024        0x6a            0x21
Mon Aug 26 18:18:26 2024        0x6b            0x40
Mon Aug 26 18:18:26 2024        0x6c            0x0
Mon Aug 26 18:18:26 2024        0x6d            0x0
Mon Aug 26 18:18:26 2024        0x6e            0x0
Mon Aug 26 18:18:26 2024        0x6f            0x0
Mon Aug 26 18:18:26 2024        0x70            0x5
Mon Aug 26 18:18:26 2024        0x71            0x23
Mon Aug 26 18:18:26 2024        0x72            0x0
Mon Aug 26 18:18:26 2024        0x73            0x0
Mon Aug 26 18:18:26 2024        0x74            0x0
Mon Aug 26 18:18:26 2024        0x75            0x0
Mon Aug 26 18:18:26 2024        0x76            0x21
Mon Aug 26 18:18:26 2024        0x77            0x1a
Mon Aug 26 18:18:26 2024        0x78            0x30
Mon Aug 26 18:18:26 2024        0x79            0x10
Mon Aug 26 18:18:26 2024        0x7a            0x0
Mon Aug 26 18:18:26 2024        0x7b            0x0
Mon Aug 26 18:18:26 2024        0x7c            0x0
Mon Aug 26 18:18:26 2024        0x7d            0x48
Mon Aug 26 18:18:26 2024        0x7e            0x13
Mon Aug 26 18:18:26 2024        0x7f            0x2a
Mon Aug 26 18:18:26 2024        0x80            0x1e
Mon Aug 26 18:18:26 2024        0x81            0xe5
Mon Aug 26 18:18:27 2024        0x82            0x0
Mon Aug 26 18:18:27 2024        0x83            0x0
Mon Aug 26 18:18:27 2024        0x84            0x34
Mon Aug 26 18:18:27 2024        0x85            0x0
Mon Aug 26 18:18:27 2024        0x86            0x0
Mon Aug 26 18:18:27 2024        0x87            0x0
Mon Aug 26 18:18:27 2024        0x88            0x0
Mon Aug 26 18:18:27 2024        0x89            0x0
Mon Aug 26 18:18:27 2024        0x8a            0x0
Mon Aug 26 18:18:27 2024        0x8b            0x0
Mon Aug 26 18:18:27 2024        0x8c            0x0
Mon Aug 26 18:18:27 2024        0x8d            0x0
Mon Aug 26 18:18:27 2024        0x8e            0x0
Mon Aug 26 18:18:27 2024        0x8f            0x40
Mon Aug 26 18:18:27 2024        0x90            0x0
Mon Aug 26 18:18:27 2024        0x91            0x0
Mon Aug 26 18:18:27 2024        0x92            0x0
Mon Aug 26 18:18:27 2024        0x93            0x0
Mon Aug 26 18:18:27 2024        0x94            0x0
Mon Aug 26 18:18:27 2024        0x95            0x0
Mon Aug 26 18:18:27 2024        0x96            0x8
Mon Aug 26 18:18:27 2024        0x97            0xff
Mon Aug 26 18:18:27 2024        0x98            0x0
Mon Aug 26 18:18:27 2024        0x99            0x3f
Mon Aug 26 18:18:27 2024        0x9a            0x3f
Mon Aug 26 18:18:27 2024        0x9b            0xe0
Mon Aug 26 18:18:27 2024        0x9c            0x24
Mon Aug 26 18:18:27 2024        0x9d            0xa5
Mon Aug 26 18:18:27 2024        0x9e            0x48
Mon Aug 26 18:18:27 2024        0x9f            0x0
Mon Aug 26 18:18:27 2024        0xa0            0x0
Mon Aug 26 18:18:27 2024        0xa1            0x40
Mon Aug 26 18:18:27 2024        0xa2            0x50
Mon Aug 26 18:18:27 2024        0xa3            0x80
Mon Aug 26 18:18:27 2024        0xa4            0x90
Mon Aug 26 18:18:27 2024        0xa5            0x20
Mon Aug 26 18:18:27 2024        0xa6            0x43
Mon Aug 26 18:18:27 2024        0xa7            0x1d
Mon Aug 26 18:18:27 2024        0xa8            0x0

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Apologies for the delay.  Is my understanding correct that you don't see this issue at 25G, but see this at 10G?  Is there a way you can look at the optical module output?

    Do you have a passive DAC you can try at 10G?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    This is used on another 10G daughter card, and feedback says that this port always has packet errors and the eye diagram of the receiving port is not good. During the period when the value of 0x27 was 4, the port did not UP. The next day when I saw it UP, the value of 0x27 was 9, but there were many error packets. I have seen other ports with error packets on 0x27 with a value of 5, and the CDR is locked. 0x78 is 0x30, and 0x2 is 0xd8
    The output from the other end is not in our data center, and we are currently unable to know the output status of the devices there.
    The wiring in the computer room is completed and all connections are made using fiber optic cables, so it is inconvenient to try changing the wiring.

    Thanks.

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    What sort of optical module are you using?  Does it have CDR, or just limiting amplifier?

    The HEO/VEO values you shared are very small, so it is not surprising that you see packet errors.  It's important for us to understand why HEO/VEO is so small.  I think we need to better understand the signal quality going to the DS280DF810.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    The optical module we are currently using contains CDR.

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    I'd like to ensure that I understand this correctly, so please help ensure my understanding is correct.  My understanding is that you have a 10G signal going from an optical module with CDR to the DS250DF810 retimer, CH5.  In this test case, you see very small eye opening on DS250DF810.

    Based on my current understanding, this is not the performance that TI would expect.  We expect that an optical module with CDR will have a very clean output.  We also expect that DS250DF810 would not have any issue with a 10G signal for a low loss case.

    You mentioned you have a 10G daughter card.  Can you help clarify how this fits into your system?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    like this.

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Thanks for clarifying.  Based on my understanding, I would expect the DS250DF810 to work well in this situation.  Because of this, I'm wondering if there is some other signal impairment, either from the optical module or the PCB layout.

    • Is there any way to look at the optical module output? Do you have a scope that can do this?  Alternatively, do you have other systems you can test this optical module with to verify that it works well?
    • Have you done any high speed analysis of the PCB traces from optical module to DS250DF810?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hi Drew，

    We have obtained on-site module testing, and on the same 10G daughter card, we have made fiber optic outer loops for two modules. Viewing the reception from the optical module to DS250DF810; The eye diagram parameters are (>0.6;>500mv), and the eye diagram image is very good;
    The on-site situation cannot be confirmed;

    Other details are being confirmed;
    The 0x27 and 0x28 parameters seen on the 10G interface with some packet errors are attached；

    “Have you done any high speed analysis of the PCB traces from optical module to DS250DF810?”

    NO；

    error-cnt-bufferparam.txt 
    ----------------------------------------------------------------------------

3/1/21	 error cnt : 20716  
========================rx buffer========================================  
 pal third i2c write 2 0xd 0 0xe8 0x48 0xff 0x1
 pal third i2c write 2 0xd 0 0xe8 0x48 0xfc 0x4
 pal third i2c read 2 0xd 0 0xe8 0x48 0x78 0x1
value: 0x      30

 pal third i2c read 2 0xd 0 0xe8 0x48 0x2 0x1
value: 0x      d8

 pal third i2c read 2 0xd 0 0xe8 0x48 0x27 0x1
value: 0x       e

 pal third i2c read 2 0xd 0 0xe8 0x48 0x28 0x1
value: 0x      a8
========================tx buffer========================================
pal third i2c write 2 0xd 0 0xe8 0x40 0xff 0x1
pal third i2c write 2 0xd 0 0xe8 0x40 0xfc 0x4
pal third i2c read 2 0xd 0 0xe8 0x40 0x78 0x1
alue: 0x      30

pal third i2c read 2 0xd 0 0xe8 0x40 0x2 0x1
alue: 0x      d8

pal third i2c read 2 0xd 0 0xe8 0x40 0x27 0x1
alue: 0x      1d

pal third i2c read 2 0xd 0 0xe8 0x40 0x28 0x1
alue: 0x      c0





----------------------------------------------------------------------------
3/1/22	  error cnt :43  
========================rx buffer========================================  
 pal third i2c write 2 0xd 0 0xe8 0x48 0xff 0x1
 pal third i2c write 2 0xd 0 0xe8 0x48 0xfc 0x8
 pal third i2c read 2 0xd 0 0xe8 0x48 0x78 0x1
value: 0x      30

 pal third i2c read 2 0xd 0 0xe8 0x48 0x2 0x1
value: 0x      d8

 pal third i2c read 2 0xd 0 0xe8 0x48 0x27 0x1
value: 0x      17

 pal third i2c read 2 0xd 0 0xe8 0x48 0x28 0x1
value: 0x      93
==============tx buffer========================================
 pal third i2c write 2 0xd 0 0xe8 0x40 0xff 0x1
 pal third i2c write 2 0xd 0 0xe8 0x40 0xfc 0x8
 pal third i2c read 2 0xd 0 0xe8 0x40 0x78 0x1
value: 0x      30

 pal third i2c read 2 0xd 0 0xe8 0x40 0x2 0x1
value: 0x      d8

 pal third i2c read 2 0xd 0 0xe8 0x40 0x27 0x1
value: 0x      1c

pal third i2c read 2 0xd 0 0xe8 0x40 0x28 0x1
alue: 0x      c0






----------------------------------------------------------------------------
3/1/33	 error cnt :14     may down
========================rx buffer========================================
pal third i2c write 2 0xc 0 0xe8 0x4c 0xff 0x1
pal third i2c write 2 0xc 0 0xe8 0x4c 0xfc 0x20

pal third i2c read 2 0xc 0 0xe8 0x4c 0x78 0x1
alue: 0x      30

pal third i2c read 2 0xc 0 0xe8 0x4c 0x2 0x1
alue: 0x      d8

pal third i2c read 2 0xc 0 0xe8 0x4c 0x27 0x1
alue: 0x       5

pal third i2c read 2 0xc 0 0xe8 0x4c 0x28 0x1
alue: 0x      24
=============tx buffer========================================
pal third i2c write 2 0xc 0 0xe8 0x46 0xff 0x1
pal third i2c write 2 0xc 0 0xe8 0x46 0xfc 0x10
al third i2c read 2 0xc 0 0xe8 0x46 0x78 0x1
alue: 0x      30

pal third i2c read 2 0xc 0 0xe8 0x46 0x2 0x1
alue: 0x      d8

pal third i2c read 2 0xc 0 0xe8 0x46 0x27 0x1
alue: 0x      1d

pal third i2c read 2 0xc 0 0xe8 0x46 0x28 0x1
alue: 0x      bc

    Thanks

  • 0 in reply to ? ??
    TI__Guru**** 156181 points

    Hi,

    Due to the US Labor Day holiday, the response to your question may be delayed. We will look into your question when we return tomorrow, Sept 3rd. Sorry for the wait and any inconvenience it may cause.

    Thanks,

    David

  • 0 in reply to David (ASIC) Liu
    TI__Mastermind 23197 points

    Hi,

    These HEO/VEO values look much better.  It's surprising that you're still seeing bit errors.

    How are you checking for bit errors?  Are you using PRBS pattern?

    Have you tried using the retimer PRBS generator/checker?  This can help you isolate which part of the link is causing bit errors.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    This is an error packet seen on the receiving port of the switching chip in the on-site network environment;
    Not running PRBS tests;
    In our local testing, the light intensity of the optical module decreased, and we did not see such a low receiving eye diagram parameter;
    I have seen several ports with incorrect packets, and the value of 0x27 is still acceptable. I am preparing to reset the CDR of ds250df810 to see if it works.
    When viewing eye diagrams through the DS250DF810, is the printed eye diagram usually one in the middle and half on both sides?

  • 0 in reply to ? ??
    TI__Mastermind 23197 points

    Hi,

    Thanks for the update.  Let us know how the testing goes.  You might also consider running PRBS tests to help identify which part of the link is creating bit errors.

    ? ?? said:
    When viewing eye diagrams through the DS250DF810, is the printed eye diagram usually one in the middle and half on both sides?

    Yes it is common to see an eye in the middle and half on both sides.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hi Drew，

    When in 10G mode, there is a phenomenon that needs to be consulted:
    The configuration items for ds250df810 have not been updated yet and are currently being debugged using script configuration.
    There is a device in the computer room with a 10G optical module that has relatively low light intensity, but obtaining the register of ds250df810 shows that the values of 0x27 and 0x28 are better. However, after several days of observation, the error packet growth on several ports is very obvious, and it is currently unknown how to completely eliminate it.

    Is there any good suggestion or direction adjustment for this?

    thanks

    10Gpor-buffer-dump.txt 
    ----------------------RX------------------------
 ---------------------------------------------
 subcard8 ds250df810 addr:30 channel:6 show shared register:
        reg_addr        value
        0x0             0x0
        0x1             0x30
        0x2             0x0
        0x3             0x0
        0x4             0x9
        0x5             0x1
        0x6             0x0
        0x7             0x0
        0x8             0x0
        0x9             0x0
        0xa             0x0
        0xb             0x40
        0xc             0x0
        0xd             0x80
        0xe             0x0
        0xf             0x0
        0x10            0xff
        0x11            0x0
        0x12            0x91
 ---------------------------------------------
 ---------------------------------------------
 subcard8 ds250df810 addr:30 channel:6 show register:
        reg_addr        value
        0x0             0x0
        0x1             0x80
        0x2             0xd8
        0x3             0x0
        0x4             0x1
        0x5             0x1
        0x6             0x1
        0x7             0x1
        0x8             0x73
        0x9             0x0
        0xa             0x0
        0xb             0x63
        0xc             0x0
        0xd             0x80
        0xe             0x93
        0xf             0x69
        0x10            0x0
        0x11            0x20
        0x12            0x83
        0x13            0xb0
        0x14            0x4
        0x15            0x10
        0x16            0x7a
        0x17            0x36
        0x18            0x40
        0x19            0x20
        0x1a            0x58
        0x1b            0x3
        0x1c            0x90
        0x1d            0x0
        0x1e            0x3
        0x1f            0xb
        0x20            0x0
        0x21            0x0
        0x22            0x0
        0x23            0x40
        0x24            0x3
        0x25            0x0
        0x26            0xb
        0x27            0x18
        0x28            0xa8
        0x29            0x60
        0x2a            0x5a
        0x2b            0xa
        0x2c            0xf6
        0x2d            0x30
        0x2e            0x0
        0x2f            0x4
        0x30            0x0
        0x31            0x40
        0x32            0x11
        0x33            0x88
        0x34            0xbf
        0x35            0xf
        0x36            0x30
        0x37            0x1
        0x38            0x10
        0x39            0x60
        0x3a            0x0
        0x3b            0x33
        0x3c            0x8e
        0x3d            0x82
        0x3e            0x41
        0x3f            0x1
        0x40            0x0
        0x41            0x40
        0x42            0x50
        0x43            0x80
        0x44            0x90
        0x45            0xc0
        0x46            0xd0
        0x47            0xd1
        0x48            0xd5
        0x49            0xd8
        0x4a            0xea
        0x4b            0xf7
        0x4c            0xfd
        0x4d            0xee
        0x4e            0xef
        0x4f            0xff
        0x50            0x0
        0x51            0x0
        0x52            0x0
        0x53            0x0
        0x54            0x0
        0x55            0x0
        0x56            0x0
        0x57            0x0
        0x58            0x0
        0x59            0x0
        0x5a            0x0
        0x5b            0x0
        0x5c            0x0
        0x5d            0x0
        0x5e            0x0
        0x5f            0x0
        0x60            0x0
        0x61            0x0
        0x62            0x0
        0x63            0x0
        0x64            0x0
        0x65            0x0
        0x66            0x0
        0x67            0x20
        0x68            0x0
        0x69            0xa
        0x6a            0x21
        0x6b            0x40
        0x6c            0x0
        0x6d            0x0
        0x6e            0x0
        0x6f            0x0
        0x70            0x5
        0x71            0x23
        0x72            0x10
        0x73            0x10
        0x74            0x10
        0x75            0x10
        0x76            0x21
        0x77            0x1a
        0x78            0x30
        0x79            0x10
        0x7a            0x0
        0x7b            0x0
        0x7c            0x0
        0x7d            0x48
        0x7e            0x13
        0x7f            0x2a
        0x80            0x1e
        0x81            0xe5
        0x82            0x0
        0x83            0x0
        0x84            0x24
        0x85            0x0
        0x86            0x0
        0x87            0x0
        0x88            0x0
        0x89            0x0
        0x8a            0x0
        0x8b            0x0
        0x8c            0x0
        0x8d            0x0
        0x8e            0x0
        0x8f            0x40
        0x90            0x0
        0x91            0x0
        0x92            0x0
        0x93            0x0
        0x94            0x0
        0x95            0x0
        0x96            0x8
        0x97            0xff
        0x98            0x0
        0x99            0x3f
        0x9a            0x3f
        0x9b            0xe0
        0x9c            0x24
        0x9d            0xa5
        0x9e            0x48
        0x9f            0x0
        0xa0            0x0
        0xa1            0x40
        0xa2            0x50
        0xa3            0x80
        0xa4            0x90
        0xa5            0x20
        0xa6            0x43
        0xa7            0x18
        0xa8            0x0
 ---------------------------------------------

---------------TX----------------------------------
 subcard8 ds250df810 addr:30 channel:6 show shared register:
        reg_addr        value
        0x0             0x0
        0x1             0x30
        0x2             0x0
        0x3             0x0
        0x4             0x9
        0x5             0x1
        0x6             0x0
        0x7             0x0
        0x8             0x0
        0x9             0x0
        0xa             0x0
        0xb             0x40
        0xc             0x0
        0xd             0x80
        0xe             0x0
        0xf             0x0
        0x10            0xff
        0x11            0x0
        0x12            0x91
 ---------------------------------------------
 ---------------------------------------------
 subcard8 ds250df810 addr:30 channel:6 show register:
        reg_addr        value
        0x0             0x0
        0x1             0x80
        0x2             0xd8
        0x3             0x0
        0x4             0x1
        0x5             0x1
        0x6             0x1
        0x7             0x1
        0x8             0x73
        0x9             0x0
        0xa             0x0
        0xb             0x63
        0xc             0x0
        0xd             0x80
        0xe             0x93
        0xf             0x69
        0x10            0x0
        0x11            0x20
        0x12            0x83
        0x13            0xb0
        0x14            0x4
        0x15            0x10
        0x16            0x7a
        0x17            0x36
        0x18            0x40
        0x19            0x20
        0x1a            0x58
        0x1b            0x3
        0x1c            0x90
        0x1d            0x0
        0x1e            0x3
        0x1f            0xb
        0x20            0x0
        0x21            0x0
        0x22            0x0
        0x23            0x40
        0x24            0x3
        0x25            0x0
        0x26            0xb
        0x27            0x17
        0x28            0xa8
        0x29            0x60
        0x2a            0x5a
        0x2b            0xa
        0x2c            0xf6
        0x2d            0x30
        0x2e            0x0
        0x2f            0x4
        0x30            0x0
        0x31            0x40
        0x32            0x11
        0x33            0x88
        0x34            0xbf
        0x35            0xf
        0x36            0x30
        0x37            0x1
        0x38            0x10
        0x39            0x60
        0x3a            0x0
        0x3b            0x33
        0x3c            0x8e
        0x3d            0x82
        0x3e            0x41
        0x3f            0x1
        0x40            0x0
        0x41            0x40
        0x42            0x50
        0x43            0x80
        0x44            0x90
        0x45            0xc0
        0x46            0xd0
        0x47            0xd1
        0x48            0xd5
        0x49            0xd8
        0x4a            0xea
        0x4b            0xf7
        0x4c            0xfd
        0x4d            0xee
        0x4e            0xef
        0x4f            0xff
        0x50            0x0
        0x51            0x0
        0x52            0x0
        0x53            0x0
        0x54            0x0
        0x55            0x0
        0x56            0x0
        0x57            0x0
        0x58            0x0
        0x59            0x0
        0x5a            0x0
        0x5b            0x0
        0x5c            0x0
        0x5d            0x0
        0x5e            0x0
        0x5f            0x0
        0x60            0x0
        0x61            0x0
        0x62            0x0
        0x63            0x0
        0x64            0x0
        0x65            0x0
        0x66            0x0
        0x67            0x20
        0x68            0x0
        0x69            0xa
        0x6a            0x21
        0x6b            0x40
        0x6c            0x0
        0x6d            0x0
        0x6e            0x0
        0x6f            0x0
        0x70            0x5
        0x71            0x23
        0x72            0x10
        0x73            0x10
        0x74            0x10
        0x75            0x10
        0x76            0x21
        0x77            0x1a
        0x78            0x30
        0x79            0x10
        0x7a            0x0
        0x7b            0x0
        0x7c            0x0
        0x7d            0x48
        0x7e            0x13
        0x7f            0x2a
        0x80            0x1e
        0x81            0xe5
        0x82            0x0
        0x83            0x0
        0x84            0x24
        0x85            0x0
        0x86            0x0
        0x87            0x0
        0x88            0x0
        0x89            0x0
        0x8a            0x0
        0x8b            0x0
        0x8c            0x0
        0x8d            0x0
        0x8e            0x0
        0x8f            0x40
        0x90            0x0
        0x91            0x0
        0x92            0x0
        0x93            0x0
        0x94            0x0
        0x95            0x0
        0x96            0x8
        0x97            0xff
        0x98            0x0
        0x99            0x3f
        0x9a            0x3f
        0x9b            0xe0
        0x9c            0x24
        0x9d            0xa5
        0x9e            0x48
        0x9f            0x0
        0xa0            0x0
        0xa1            0x40
        0xa2            0x50
        0xa3            0x80
        0xa4            0x90
        0xa5            0x20
        0xa6            0x43
        0xa7            0x17
        0xa8            0x0

==============================================================================================================other port

-------------------------RX-----------------------------------
subcard8 ds250df810 addr:36 channel:2 show shared register:
       reg_addr        value
       0x0             0x0
       0x1             0x50
       0x2             0x0
       0x3             0x0
       0x4             0x9
       0x5             0x81
       0x6             0x0
       0x7             0x0
       0x8             0x0
       0x9             0x0
       0xa             0x0
       0xb             0x40
       0xc             0x0
       0xd             0x48
       0xe             0x0
       0xf             0x0
       0x10            0xff
       0x11            0x0
       0x12            0x91
---------------------------------------------
---------------------------------------------
subcard8 ds250df810 addr:36 channel:2 show register:
       reg_addr        value
       0x0             0x0
       0x1             0x80
       0x2             0xd8
       0x3             0x0
       0x4             0x1
       0x5             0x1
       0x6             0x1
       0x7             0x1
       0x8             0x73
       0x9             0x0
       0xa             0x0
       0xb             0x63
       0xc             0x0
       0xd             0x80
       0xe             0x93
       0xf             0x69
       0x10            0x0
       0x11            0x20
       0x12            0x83
       0x13            0xb0
       0x14            0x4
       0x15            0x10
       0x16            0x7a
       0x17            0x36
       0x18            0x40
       0x19            0x20
       0x1a            0x58
       0x1b            0x3
       0x1c            0x90
       0x1d            0x0
       0x1e            0x3
       0x1f            0xb
       0x20            0x0
       0x21            0x0
       0x22            0x0
       0x23            0x40
       0x24            0x3
       0x25            0x0
       0x26            0x0
       0x27            0x13
       0x28            0xa8
       0x29            0x40
       0x2a            0x5a
       0x2b            0xa
       0x2c            0xf6
       0x2d            0x30
       0x2e            0x0
       0x2f            0x4
       0x30            0x0
       0x31            0x40
       0x32            0x11
       0x33            0x88
       0x34            0xbf
       0x35            0xf
       0x36            0x30
       0x37            0x0
       0x38            0x10
       0x39            0x60
       0x3a            0x0
       0x3b            0x33
       0x3c            0x8d
       0x3d            0x82
       0x3e            0x41
       0x3f            0x1
       0x40            0x0
       0x41            0x40
       0x42            0x50
       0x43            0x80
       0x44            0x90
       0x45            0xc0
       0x46            0xd0
       0x47            0xd1
       0x48            0xd5
       0x49            0xd8
       0x4a            0xea
       0x4b            0xf7
       0x4c            0xfd
       0x4d            0xee
       0x4e            0xef
       0x4f            0xff
       0x50            0x0
       0x51            0x0
       0x52            0x0
       0x53            0x0
       0x54            0x0
       0x55            0x0
       0x56            0x0
       0x57            0x0
       0x58            0x0
       0x59            0x0
       0x5a            0x0
       0x5b            0x0
       0x5c            0x0
       0x5d            0x0
       0x5e            0x0
       0x5f            0x0
       0x60            0x0
       0x61            0x0
       0x62            0x0
       0x63            0x0
       0x64            0x0
       0x65            0x0
       0x66            0x0
       0x67            0x20
       0x68            0x0
       0x69            0xa
       0x6a            0x21
       0x6b            0x40
       0x6c            0x0
       0x6d            0x0
       0x6e            0x0
       0x6f            0x0
       0x70            0x5
       0x71            0x24
       0x72            0x10
       0x73            0x11
       0x74            0x10
       0x75            0x10
       0x76            0x21
       0x77            0x1a
       0x78            0x30
       0x79            0x10
       0x7a            0x0
       0x7b            0x0
       0x7c            0x0
       0x7d            0x48
       0x7e            0x13
       0x7f            0x2a
       0x80            0x1e
       0x81            0xe5
       0x82            0x0
       0x83            0x0
       0x84            0x20
       0x85            0x0
       0x86            0x0
       0x87            0x0
       0x88            0x0
       0x89            0x0
       0x8a            0x0
       0x8b            0x0
       0x8c            0x0
       0x8d            0x0
       0x8e            0x0
       0x8f            0x0
       0x90            0x0
       0x91            0x0
       0x92            0x0
       0x93            0x0
       0x94            0x0
       0x95            0x0
       0x96            0x8
       0x97            0xff
       0x98            0x0
       0x99            0x3f
       0x9a            0x3f
       0x9b            0xe0
       0x9c            0x24
       0x9d            0xa5
       0x9e            0x48
       0x9f            0x0
       0xa0            0x0
       0xa1            0x40
       0xa2            0x50
       0xa3            0x80
       0xa4            0x90
       0xa5            0x20
       0xa6            0x43
       0xa7            0x13
       0xa8            0x0
---------------------------------------------

-----------------TX-------------------------------------------
---------------------------------------------
subcard8 ds250df810 addr:34 channel:2 show shared register:
       reg_addr        value
       0x0             0x0
       0x1             0x30
       0x2             0x0
       0x3             0x0
       0x4             0x9
       0x5             0x81
       0x6             0x0
       0x7             0x0
       0x8             0x0
       0x9             0x0
       0xa             0x0
       0xb             0x40
       0xc             0x0
       0xd             0x5
       0xe             0x0
       0xf             0x0
       0x10            0xff
       0x11            0x0
       0x12            0x91
---------------------------------------------
---------------------------------------------
subcard8 ds250df810 addr:34 channel:2 show register:
       reg_addr        value
       0x0             0x0
       0x1             0x80
       0x2             0xd8
       0x3             0x0
       0x4             0x1
       0x5             0x1
       0x6             0x1
       0x7             0x1
       0x8             0x73
       0x9             0x0
       0xa             0x0
       0xb             0x63
       0xc             0x0
       0xd             0x80
       0xe             0x93
       0xf             0x69
       0x10            0x0
       0x11            0x20
       0x12            0x83
       0x13            0xb0
       0x14            0x4
       0x15            0x10
       0x16            0x7a
       0x17            0x36
       0x18            0x40
       0x19            0x20
       0x1a            0x58
       0x1b            0x3
       0x1c            0x90
       0x1d            0x0
       0x1e            0xe9
       0x1f            0xb
       0x20            0x0
       0x21            0x0
       0x22            0x0
       0x23            0x40
       0x24            0x3
       0x25            0x0
       0x26            0x0
       0x27            0x1d
       0x28            0xbc
       0x29            0x60
       0x2a            0x5a
       0x2b            0xa
       0x2c            0xf6
       0x2d            0x30
       0x2e            0x0
       0x2f            0x4
       0x30            0x0
       0x31            0x20
       0x32            0x11
       0x33            0x88
       0x34            0xbf
       0x35            0xf
       0x36            0x30
       0x37            0x1
       0x38            0x0
       0x39            0x60
       0x3a            0x0
       0x3b            0x33
       0x3c            0x8d
       0x3d            0x88
       0x3e            0x41
       0x3f            0x2
       0x40            0x0
       0x41            0x40
       0x42            0x50
       0x43            0x80
       0x44            0x90
       0x45            0xc0
       0x46            0xd0
       0x47            0xd1
       0x48            0xd5
       0x49            0xd8
       0x4a            0xea
       0x4b            0xf7
       0x4c            0xfd
       0x4d            0xee
       0x4e            0xef
       0x4f            0xff
       0x50            0x0
       0x51            0x0
       0x52            0x0
       0x53            0x0
       0x54            0x0
       0x55            0x0
       0x56            0x0
       0x57            0x0
       0x58            0x0
       0x59            0x0
       0x5a            0x0
       0x5b            0x0
       0x5c            0x0
       0x5d            0x0
       0x5e            0x0
       0x5f            0x0
       0x60            0x0
       0x61            0x0
       0x62            0x0
       0x63            0x0
       0x64            0x0
       0x65            0x0
       0x66            0x0
       0x67            0x20
       0x68            0x0
       0x69            0xa
       0x6a            0x21
       0x6b            0x40
       0x6c            0x0
       0x6d            0x0
       0x6e            0x0
       0x6f            0x0
       0x70            0x5
       0x71            0x23
       0x72            0x0
       0x73            0x0
       0x74            0x0
       0x75            0x0
       0x76            0x21
       0x77            0x1a
       0x78            0x30
       0x79            0x10
       0x7a            0x0
       0x7b            0x0
       0x7c            0x0
       0x7d            0x48
       0x7e            0x13
       0x7f            0x2a
       0x80            0x0
       0x81            0xe5
       0x82            0x0
       0x83            0x0
       0x84            0x0
       0x85            0x0
       0x86            0x0
       0x87            0x0
       0x88            0x0
       0x89            0x0
       0x8a            0x0
       0x8b            0x0
       0x8c            0x0
       0x8d            0x0
       0x8e            0x0
       0x8f            0x40
       0x90            0x0
       0x91            0x0
       0x92            0x0
       0x93            0x0
       0x94            0x0
       0x95            0x0
       0x96            0x8
       0x97            0xff
       0x98            0x0
       0x99            0x3f
       0x9a            0x3f
       0x9b            0xe0
       0x9c            0x24
       0x9d            0xa5
       0x9e            0x48
       0x9f            0x0
       0xa0            0x0
       0xa1            0x40
       0xa2            0x50
       0xa3            0x80
       0xa4            0x90
       0xa5            0x20
       0xa6            0x43
       0xa7            0x1d
       0xa8            0x0

  • 0 in reply to ? ??
    TI__Mastermind 19640 points

    Hi,

    Drew is currently out of office so I will be taking over support in his place.

    Allow me to review your register dump and provide feedback by early next week.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

     Hi Lucas Wolter
    I found several 10G ports with packet errors, with values in 0x28 being relatively large>0xa0, and 0x27 generally>0x14
    The distance from the optical module to DS250DF810 rx should be 3-4 inches.
    When I use adapt mode 2, resetting the switch chip's own port may also lead to further deterioration; A good port won't have this problem. Do I need to reset the interface of the DS250df810 after switch chips.

  • 0 in reply to ? ??
    TI__Mastermind 19640 points

    Hi,

    Thank you for the summary. I will review your register dump and provide feedback by COB tomorrow, 9/10 US time.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Hi Lucas
    When we debug the 10G interface on site, we debug the ds250df810 on the receiving path and the CTLE on the switching chip.
    The ds250df810 will initialize first, followed by switching chips.
    Some interfaces may detect erroneous packets, and resetting the receiving end of the switch chip will cause the erroneous packets to disappear;
    I reconfigured the parameters of this channel on DS250DF810 for some interfaces, and the CDR was reset or de reset, resulting in the disappearance of error packets.
    Several ports of the switch chip's receiving port have been reset, and the DS250DF810 has also been reset, resulting in a slow increase in error packets.
    I feel that there are some differences between the automatic adaptation of CTLE at the receiving port of ds250ds810 and the switch chip, and it is sometimes difficult to reach a consensus.
    Is there any good way to do this?
    Thank you.

  • 0 in reply to ? ??
    TI__Mastermind 19640 points

    Hi,

    Is it possible to wait until DS250DF810 adaptation is complete, then reset the switch chip to re-trigger the switch chip's CTLE adaptation? The goal would be to allow the switch chip CTLE adaptation to take place after the retimer configuration has already settled into a steady state.

    Best,

    Lucas