DP83822I: Behavior when VDDIO or/and AVD exceed 0.3V before powering up

Hello Gerome-san,

Thank you for your reply.
>According to section 7.6, this constraint is due to best practice to avoid false detection of VDDIO. This can be cross verified by checking Reg 0x421 to >ensure PHY accurately captured the appropriate voltage and is in the respective mode. If anything is awry, user may adjust using Reg 0x41F.
Understood. However, what I would like you to confirm is what behavior will happen when VDDIO and/or AVD exceed 0.3V before powering up.
Could you please comment about this ?

Best Regards

Hello,

Usually tell-tale signs of this behavior being apparent is PHY not linking up. Is customer seeing this in their design?

Sincerely,

Gerome

Hi,

>Usually tell-tale signs of this behavior being apparent is PHY not linking up. Is customer seeing this in their design?
Yes, they observed link up issue.
After they observed link up issue, they investigated root cause of this issue, then they notice that FLP(fast link pulse) was different from normal behavior (Normal behavior means they observe link up correctly).
It seems that this may be root cause of link up issue, however they could not connect to anything, why this was observed.
Can you explain relationship between "VDDIO and/or AVD exceed 0.3V before powering up" and "link up issue" ?

Best Regards,

Hello,

If this spec is violated, there is chance that PHY does not detect the correct VDDA and/or VDDIO level. This would cause misbehavior on the PHY which can include link issues.

If customer sees this issue, can they please check Reg 0x41F and 0x421?

Sincerely,

Gerome

Hello,

Thank you for your reply.
Understood. And also, I will ask customer about what register value they can get when link up issue is observed.

BR,

Hello,

>If customer sees this issue, can they please check Reg 0x41F and 0x421?
My customer sent us register value for both case of linking up issue and case of normal behavior.

1. Case of Normal behavior
Reg 0x41F：0x0000 (Same value is observed "before" and "after" linking up.)
Reg 0x421：0x7849 (Before linking up) -> 0x786d (After linking up)

2. Case of linking up issue
Reg 0x41F：0x0000
Reg 0x421：0x7849

What do you think about this result ?

BR,

Hello,

Can customer please confirm they are using extended register access to read these registers per datasheet and this FAQ?

Sincerely,

Gerome

Hello,

Let me confirm whether my understanding is correct or not.

* What you would like us to confirm is customer need to access address 0x41F and address 0x421 by following below FAQ again.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1271487/faq-extended-register-space-access-for-ethernet-phys?tisearch=e2e-sitesearch&keymatch=%252525252520user%25252525253A526529
Is my understanding correct ?

Best Regards,

Hello,

Yes, this is correct. I am concerned that the register logs shared are not valid due to in-appropriate register access and want to double check if this 4-step register read process has been followed or not by customer.

Sincerely,

Gerome

Hello,

I asked customer to follow your suggested method. And I got following result.

1. Case of linking up issue
Reg 0x41F：0x0000
Reg 0x421：0x0000


2. Case of Normal behavior
Reg 0x41F：0x0000
Reg 0x421：0x0007 (This shows expected voltage)

Then, let me confirm whether my following understanding is "correct" or "not".

* 
1. ”This would cause misbehavior on the PHY which can include link issues.”
    One of above Link issue cause abnormal link pulse output comparing to normal(Linkup is established) behavior.
2. If above my understanding is correct, this link pulse issue cause due to at least “AVD and VDDIO exceed 0.3 V prior to supply ramp.”
    In other words, customer never observe this issue as long as they operate under recommended environment/recommended operating condition which is described in datasheet.

Thanks in advance,