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DS100DF410: input signal requirement for CDR locking

Part Number: DS100DF410
Other Parts Discussed in Thread: DS125DF1610, DS125DF111

Tool/software:

Hi,

Below is copied from the another post, are these the same input signal requirement for DS100DF410 CDR locking? Thank you!

Here are some possibilities for the ds125df1610 CDR not locking.

  • Signal data-rate incompatible with retimer
  • Invalid signal sub-rate is being used
  • Valid signal sub-rate is being used (div2/4/8), but device DS125DF1610 register config is not set to the proper sub-rate
  • Signal does not have a high enough density of bit transitions for CDR to lock ( channel register 0x0C[3] )
  • Signal does not meet PPM check criteria ( channel register 0x2F[2] )
  • Insertion loss at receiver end exceeds the maximum EQ of the retimer

Best,

Zach

  • Hi Zach,

    Reasons for CDR not locking are a bit different on DS100DF410 because this retimer can only lock to 10.3125 Gbps and 1.25 Gbps.

    • Signal data rate incompatible with retimer
    • Signal does not have a high enough density of bit transitions for CDR to lock (channel register 0x0C[3])
    • Signal does not meet PPM check criteria (channel register 0x2F[2])
    • Insertion loss at receiver end exceeds the maximum EQ of the retimer
    • Signal quality and amplitude level is not sufficient for lock
    • HEO and VEO do not meet the required threshold for lock (channel register 0x3E[7])

    Best,

    Lucas

  • Hi Lucas.

    Could the CDR lock to 8081 codesquare wave)?

  • Hi Zach,

    DS100DF410 CDR can lock to 10.3125 Gbps 8180 pattern (equivalent to 644.53125 MHz square wave) if you write 0x0C[3]=0. De-asserting this bit disables single bit limit check, which removes the density of bit transitions as a gating factor to obtain CDR lock. I confirmed I could get CDR lock in a bench experiment.

    Best,

    Lucas

  • HI Lucas,

    The datasheet of DS100DF410 does not mention this bit. But I find it in DS125DF111.

    Can you explain how Single Bit Transition Detector works? Does it require no continuous  0 or 1, or how much transition density is required?

    And during normal operation, must customer enable it? 

  • Hi Zach,

    The single bit transition detector measures the number of transitions from 1 to 0 or 0 to 1 in a certain period of time. The purpose is to confirm the data is 10.3125 Gbps, and not a sub-rate such as 5.15625 Gbps or 2.578125 Gbps. A 101010 pattern at 2.578125 Gbps looks the same as a 110011001100 pattern at 5.15625 Gbps and 111100001111000011110000 pattern at 10.3125 Gbps.

    The single bit transition detector is a gating factor to achieving CDR lock. If it determines there are not enough bit transitions and the pattern is likely transmitted at a sub-rate, then it will prevent CDR from locking. SBT detector can optionally be disabled by writing 0x0C[3]=0. If the retimer will never receive data at a sub-rate frequency during normal operation, the SBT can be disabled with no negative impact.

    Best,

    Lucas

  • Hi Lucas,

    Would it be possible to add the description of Single Bit Transition Detector in the datasheet of DS100DF410? 

    Customer say the datasheet tell it can support 1GbE but does NOT mention Single Bit Transition Detector at all.

    Thank you!

  • Hi Zach,

    Adding description of the single bit transition detector to the datasheet is under consideration. Typically we wait until several changes are necessary to revise the datasheet.

    In case it wasn't clear, DS100DF410 does support both 10.3125 Gbps and 1.25 Gbps.

    Best,

    Lucas

  • Hi Lucas,

    So what's the benefit of the SBT detector from system level? 

    The single bit transition detector is a gating factor to achieving CDR lock. If it determines there are not enough bit transitions and the pattern is likely transmitted at a sub-rate, then it will prevent CDR from locking. SBT detector can optionally be disabled by writing 0x0C[3]=0. If the retimer will never receive data at a sub-rate frequency during normal operation, the SBT can be disabled with no negative impact.

    Best,

    Zach

  • Hi Zach,

    From a system level, SBT can help ensure that the retimer is locking to the correct data rate and not a sub-rate.  Typically it is not necessary to adjust SBT bit in a system implementation, but disabling SBT check is necessary when there is a low number of bit transitions, such as in 8180 test pattern.

    Thanks,

    Drew