DS90UB948-Q1: 947设置Single link & Dual-pixel mode，打lvds信号给948，948出现异常，无法识别和读写

现在 0x5B DUAL_CTL1 寄存器的 FORCE_LINK 是默认值【0】- Auto-Detect FPD-Link III mode

947_modesel_0: 10

947_modesel_1: 00 

948_modesel_0: 100 [Dual OLDI output]

948_modesel_1: 010 [20Mbps STP]

Hi Tao,

Using a translator, it is hard to understand what you are asking. If possible, I would appreciate it if you could reach out to an local FAE and have them ask your question, or if you could re-state your question in English, that way we can better understand what you are asking about.

Best,

Josh

Hi Baik,

Thank you for your reply. I will re-state my question in English.

DS90UB948-Q1: 947 sets the Single link & Dual-pixel mode, sends lvds signal to 948,948 is abnormal, cannot identify and read and write.

case1: for 947, set the Single link & Dual-pixel mode and sends lvds signal to 948, but 948 cannot be identified or read or written

case2: for 947, set the Single link & Single-pixel mode and sends lvds signal to 948,  948 can be identified or read or written, but the display has no image

Registers infos of 947&948 have been listed previously.

Some infos for setting:

947 - register 0x5B DUAL_CTL1, set as default, Auto-Detect FPD-Link III mode

947_modesel_0: 10

947_modesel_1: 00 

948_modesel_0: 100 [Dual OLDI output]

948_modesel_1: 010 [20Mbps STP]

According to the requirements of the screen, it should be set to Dual-pixel mode.

So, please help to check this issue.

Thanks.

I also did psttern test of 948, but no no image came out.

panel-timing {
clock-frequency = <93600000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <70>;
hback-porch = <47>;
hsync-len = <43>;
vsync-len = <3>;
vfront-porch = <3>;
vback-porch = <24>;
vsync-active = <0>;
hsync-active = <0>;
};

------------------------------------------------

i2cset -f -y 3 0x34 0x66 0x03
i2cset -f -y 3 0x34 0x67 0x02
i2cset -f -y 3 0x34 0x66 0x07
i2cset -f -y 3 0x34 0x67 0x80
i2cset -f -y 3 0x34 0x66 0x08
i2cset -f -y 3 0x34 0x67 0x07
i2cset -f -y 3 0x34 0x66 0x09
i2cset -f -y 3 0x34 0x67 0x2D
i2cset -f -y 3 0x34 0x66 0x04
i2cset -f -y 3 0x34 0x67 0x20
i2cset -f -y 3 0x34 0x66 0x05
i2cset -f -y 3 0x34 0x67 0xE8
i2cset -f -y 3 0x34 0x66 0x06
i2cset -f -y 3 0x34 0x67 0x2E
i2cset -f -y 3 0x34 0x66 0x0C
i2cset -f -y 3 0x34 0x67 0x2F
i2cset -f -y 3 0x34 0x66 0x0D
i2cset -f -y 3 0x34 0x67 0x18
i2cset -f -y 3 0x34 0x66 0x0A
i2cset -f -y 3 0x34 0x67 0x2B
i2cset -f -y 3 0x34 0x66 0x0B
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x66 0x0E
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x65 0x03
i2cset -f -y 3 0x34 0x64 0x11

After did pattern test, the LOCK-PIN1 of 948 is high(3.3V). 

But no image came out.

Hi Tao,

Have you verified the timing via PATGEN on 948? It is recommended to first start with DES pattern test, verify the target timing and no system-level display-side issues, then work back towards SER side by doing SER pattern test, then finally OLDI end to end from. I would recommend the following steps for video control/timing source:

1. Deserializer PATGEN
   1. Internal - Internal timing source / Internal PCLK
   2. Internal timing source / External PCLK
   3. External - External timing source / External PCLK
2. Serializer PATGEN
   1. Internal - Internal timing source / Internal PCLK
   2. Internal timing source / External PCLK
   3. External - External timing source / External PCLK

Best,

Josh

Hi Baik,

Thank for your reply.

I did pattern test on 948, but directly set in system used i2cset command, not used USB2ANY tool.

Could you help to check my test?

---------------------------------------------------

panel-timing {
clock-frequency = <93600000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <70>;
hback-porch = <47>;
hsync-len = <43>;
vsync-len = <3>;
vfront-porch = <3>;
vback-porch = <24>;
vsync-active = <0>;
hsync-active = <0>;
};

------------------------------------------------

Take the first line as an example:

0x34 is 948's i2c slave address, 0x66 is register's address, 0x03 is setting value.

i2cset -f -y 3 0x34 0x66 0x03
i2cset -f -y 3 0x34 0x67 0x02
i2cset -f -y 3 0x34 0x66 0x07
i2cset -f -y 3 0x34 0x67 0x80
i2cset -f -y 3 0x34 0x66 0x08
i2cset -f -y 3 0x34 0x67 0x07
i2cset -f -y 3 0x34 0x66 0x09
i2cset -f -y 3 0x34 0x67 0x2D
i2cset -f -y 3 0x34 0x66 0x04
i2cset -f -y 3 0x34 0x67 0x20
i2cset -f -y 3 0x34 0x66 0x05
i2cset -f -y 3 0x34 0x67 0xE8
i2cset -f -y 3 0x34 0x66 0x06
i2cset -f -y 3 0x34 0x67 0x2E
i2cset -f -y 3 0x34 0x66 0x0C
i2cset -f -y 3 0x34 0x67 0x2F
i2cset -f -y 3 0x34 0x66 0x0D
i2cset -f -y 3 0x34 0x67 0x18
i2cset -f -y 3 0x34 0x66 0x0A
i2cset -f -y 3 0x34 0x67 0x2B
i2cset -f -y 3 0x34 0x66 0x0B
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x66 0x0E
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x65 0x03
i2cset -f -y 3 0x34 0x64 0x11

------------------------------------------------

Cause I don't have USB2ANY tool, so can you help to generate a pattern test script of 948 for me according to the panel-timing I listed?

Thanks.

Sorry， Update the panel timing.

So can provide a script for 948's pattern test?

 Hi Tao,

Could you clarify about horizontal blanking? It should be double because it is from 960 to 1920? Are you trying the pattern generator with internal timing?

In the meantime, please check the app note that is provided the configuration examples (custom display configuration or external clock example configuration): Link

Best,

Josh

Hi Baik,

Confirmed with panel supplier, the lvds timing shown as below:

panel-timing {
clock-frequency = <93657420>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <70>;
hback-porch = <84>;
hsync-len = <24>;
vsync-len = <3>;
vfront-porch = <11>;
vback-porch = <10>;
vsync-active = <0>;
hsync-active = <0>;
};

And I did the pattern test(custom display configuration) on 948 refer to app note.

The LOCK PIN is high, but no image came out.

i2cset -f -y 3 0x34 0x66 0x03
i2cset -f -y 3 0x34 0x67 0x02
i2cset -f -y 3 0x34 0x66 0x07
i2cset -f -y 3 0x34 0x67 0x80
i2cset -f -y 3 0x34 0x66 0x08
i2cset -f -y 3 0x34 0x67 0x07
i2cset -f -y 3 0x34 0x66 0x09
i2cset -f -y 3 0x34 0x67 0x2D
i2cset -f -y 3 0x34 0x66 0x04
i2cset -f -y 3 0x34 0x67 0x32
i2cset -f -y 3 0x34 0x66 0x05
i2cset -f -y 3 0x34 0x67 0x88
i2cset -f -y 3 0x34 0x66 0x06
i2cset -f -y 3 0x34 0x67 0x2E
i2cset -f -y 3 0x34 0x66 0x0C
i2cset -f -y 3 0x34 0x67 0x54
i2cset -f -y 3 0x34 0x66 0x0D
i2cset -f -y 3 0x34 0x67 0x0A
i2cset -f -y 3 0x34 0x66 0x0A
i2cset -f -y 3 0x34 0x67 0x18
i2cset -f -y 3 0x34 0x66 0x0B
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x66 0x0E
i2cset -f -y 3 0x34 0x67 0x03
i2cset -f -y 3 0x34 0x65 0x03
i2cset -f -y 3 0x34 0x64 0x11

Are there any points need to check?

Thanks.

Hi Tao,

The PATGEN programming is right for the desired timing. Could you please check if the code mentioned in 947 has been written? The code is required to follow the power-up sequence. You can see this thread for your reference: Link

Best,

Josh