DS90UB941AS-Q1: Several questions about the Mode and clock

Hi Andy,

Andy Jin said:

1） If use the Dual FPD-Link III mode, does it need use the 2x 4Lane MIPI DSI input?    DSI0 and DSI1. 

When using Dual FPD-Link III mode, this increases the data rate between the SER and DES devices, meaning the Pixel Clock can support up to 210 MHz (3.675 Gbps x 2).

The DSI port supports 4 lanes at 1.5 Gbps per lane, so one port can support 6 Gbps, 2 ports would be up to 12 Gbps. The DSI Rates also depend on Burst mode and non burst mode, please see "2.2 Clocking Rates and Clock Type" of this app note for more details: DS90UB941AS-Q1 DSI Bringup Guide (ti.com)

The max required data rate through the DSI lanes depends on the PCLK used in the FPD-Link as well, this should be the determining factor for determining the bandwidth.

Andy Jin said:

2)   When is the external reference clock REFCLK used? Is it recommended to use an internal or external reference clock? What should I be aware of if I don't use the external reference clock REFCLK?  For REFCLK0 whether it corresponds to DSI0? For REFCLK1, whether it corresponds to DSI1?

An external REFCLK is used for synchronizing the incoming data to the serializer as the DSI PCLK, DSI reference clock is the most straightforward configuration, but an external oscillator may also be used if it is matched to the SoC DSI PCLK rate.

Internal reference clock is typically used for debug purposes only, including pattern generation with built-in self testing configurations. This could be used for example for just testing the Serializer > Deserializer > Display setup.

REFCLK0 corresponds to FPD-Link Port 0, REFCLK1 corresponds to FPD-Link Port 1. Different REFCLKs are used when in independent mode, with two different resolutions - see the example below:

In the same bring up app note linked above, this is also further explained in the same "2.2 Clocking Rates and Clock Type".

Andy Jin said:

3) How to choose Clock Modes? For 4lane's MIPI CSI, Dual FPD-Link III mode, what modes are recommended for MODE_SEL0, MODE_SEL1 in the Table8-9 and Table8-10? The display deserializer is DS90UB948-Q1 and uses dual Open LDI mode. 

Clock modes are better explained in DS90UB941AS-Q1 DSI Bringup Guide (ti.com), for the strap configurations, since this is a dual end-to-end 941AS to 948 correlates to MODE_SEL0 = 3, and MODE_SEL1 = 0.

MODE_SEL1 will either be 0 or 4, depending on if the configuration uses the DSI CLK (Mode No. 0) or an external oscillator (Mode No. 4).

Andy Jin said:

4）What are the two models of SPLITTER Mode and DISABLE DSI? 

These columns correlate to whether splitter mode is enabled, and if DSI output is disabled or not upon startup.

Splitter mode splits the video into odd/even pixels to each FPD-Link III output port. Splitter is different from independent mode, in the case that images must have identical video format (lines, pixels, blanking intervals), pixel clock but be twice the frequency needed for a single image, and other considerations. See "8.4.4.1 Left/Right 3D Format Support" of the 941AS datasheet for more details: DS90UB941AS-Q1 DSI to FPD-Link III Bridge Serializer datasheet (Rev. C) (ti.com).

DSI disable is an option in some cases where the inputs need to be configured or re-configured while the output is disabled.

Please let me know if you have any further inquiries on this, hope this helps!

Best,

Miguel