DS90C383: Jitter addition for the clock signal

Hi Ohad,

What's the application for the DS90C383 in this situation? How long is the channel between the LVDS output and the TCON (board to board connection, cable length, etc.)? It is expected that the DS90C383 will introduce some jitter but the channel will also introduce jitter.

Ohad Bonneh said:

Im inserting a clock with reasonable jitter – 200ps but at the output, they are seeing around 600ps of jitter.

What clock frequency is this?

Ohad Bonneh said:

Even after improving the input jitter i still see relatively high jitter at the output.

What was the difference you saw?

Ohad Bonneh said:

Im using our DS90C382 device in order to convert RGB to LVDS,

Just to confirm, this is the DS90C383 right?

Best,

Jack

yes it is the 383

Hi Team, 

I will try to explain the system setup better: 
We are sending to the device RGB data directly from the FPGA, 

when measuring the jitter to the input of the device on the diff clock we see 200ps of jitter. 

when measuring the jitter at the output of the diff clock we are measuring 600ps of jitter (needles to say that there is termination resistor of 100 Ohm) 

when using a different device to make sure ours isn't malfunction we are getting the same results. 

what could be the issue?   

Hi Ohad,

I'll be back with you shortly.

Best,

Jack

Hi Ohad,

Ohad Bonneh said:

when measuring the jitter at the output of the diff clock we are measuring 600ps of jitter (needles to say that there is termination resistor of 100 Ohm) 

What is the output of the diff clock connected to? Is there a LVDS receiver or a TCON that uses this data? Even if you do have a 100Ω termination, there still could be reflections caused by impedance discontinuities. 

How are you measuring the jitter? Is this cycle to cycle jitter, TIE, period jitter?

The datasheet does define cycle-to-cycle as less than 250ps at 65MHz. Note that ISI can also affect jitter depending on the interconnect.

Has this 600ps jitter been tied to any screen issues?

Best,

Jack

Hi Jack, 

we have pulled up the clock legs to make sure that we are having perfect matching, and we still see 600ps jitter at the output. 

the jitter is seen as black and blue dots on the screen and smudged picture as can be seen here: 

Hi Ohad,

Thank you for the schematic and the display picture.

Ohad Bonneh said:

we have pulled up the clock legs to make sure that we are having perfect matching

What does this mean exactly?

Ohad Bonneh said:

we still see 600ps jitter at the output. 

What type of jitter are using measuring (cycle-to-cycle, period, etc)?

Ohad Bonneh said:

the jitter is seen as black and blue dots on the screen and smudged picture as can be seen here: 

Can we get the video source to output a set pattern? I see black dots in the "FAIL" regions but everything else looks fine. 

Are the LVDS signals sent directly to the display? Also, do you know the video PCLK in this case? 

Best,

Jack