Tool/software:
Dear team,
I have question regarding IO_MUX_CFG Register (Offset = 170h) [Reset = 0CX0h] value.
1. Red box, What does "X" mean as a reset value? What is default value of bit 6 (CLK_O_DISABLE) after reset? Do I have to be set 0h or 1h after reset?
2. Green box, "Reg 0xC6 must be set equal to 0x10 before CLK_O_SEL can be modified"
What is Reg 0xC6 register? C6h is ANA_PLL_PROG_PI, reserved register with [Reset = 0000h] value. Does Reg 0xC6 mean ANA_PLL_PROG_PI? Do I have to be set equal to 0x10 before CLK_O_SEL can be modified?
3. The customer would like to use clock output of 1st DP83869HM as a clock input for 2nd DP83869HM. Is there any side effect like jitter or other problem? Is there anything I need to be careful about to use this concept?
Thank you.
