DS90UB947-Q1: Changing UB947 with external timing mode then UB948 is getting out of lock

Hi Kexiang,

If you have internal patgen with internal timing working then when you switch to external timing mode then you lose lock, there is one of 2 things happening. 

1. Your external timing or clock is not working as expected from SoC (Video source) 
2. Or you are switching between these modes on the fly so running one mode then switch to another without full power cycle and re-init (This is not supported) 

You need to run external mode at power-up you can't switch on the fly from a different mode. 

Also, which mode are you trying to switch to? External or Internal with external clock?

Regards,
Fadi A.

Hi Fadi,

Hi Fadi,

Now I have narrowed down the issue with less code. In any case, I have attempted all scenarios, but the external clock fails to function.

DSUB947_Write(0x40,0x10); // select OLDI register
DSUB947_Write(0x41,0x49); // force PLL controller in PPM reset state
DSUB947_Write(0x42,0x16);
DSUB947_Write(0x41,0x47); // force PLL LOCK Low
DSUB947_Write(0x42,0x20);
DSUB947_Write(0x42,0xA0); // reset PLL divider
DSUB947_Write(0x42,0x20);
DSUB947_Write(0x42,0x00); // release PLL LOCK control
DSUB947_Write(0x41,0x49);
DSUB947_Write(0x42,0x00); // release PLL state control
delay_ms(10);

DSUB947_Write(0x65, 0x04); //internal clock OK
//DSUB947_Write(0x65, 0x0C); //external clock NOK
DSUB947_Write(0x64, 0x05); // enable patgen

DSUB947_Write( 0x03, 0xDA);
DSUB947_Write(0x5B,0x03); //Force dual FPD-Link, disable reset on PLL frequency change
DSUB947_Write(0x16,0x02); //Adjust BCC watchdog timer to minimum
DSUB947_Write(0x04,0x90); //Prevent AVMUTE for non-HDCP systems

do { delay_ms(10); } while ((DSUB948_ReadBytes(I2C_ADDR_DSUB948, 0x1c)&0x13) != 0x13);

Regards,

Kexiang

Hi Kexiang,

For internal timing with external clock mode you still need to program the internal timing - Please see example script below. If this doesn't work that mean you have an issue with your SoC clock since this mode uses an external clock to generate the pattern. So if you don't see Lock or video that means your external clock has some issue. 

#Setting up internal CLK divider to 100Mhz (This only applies to internal timing mode)
board.WriteI2C(Ser_addr,0x66,0x1A)
board.WriteI2C(Ser_addr,0x67,0x01) #M=1
board.WriteI2C(Ser_addr,0x66,0x03)
board.WriteI2C(Ser_addr,0x67,0x02) #N=2

#Setting up Display Timing based on Customer Panel
board.WriteI2C(Ser_addr,0x66,0x04)
board.WriteI2C(Ser_addr,0x67,0x72) #least 8 bit of Total Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x05)
board.WriteI2C(Ser_addr,0x67,0xE6) #Least 4 bit TV + Most 4 bit TH
board.WriteI2C(Ser_addr,0x66,0x06)
board.WriteI2C(Ser_addr,0x67,0x31) #Most 8 bit of Total Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x07)
board.WriteI2C(Ser_addr,0x67,0x00) #least 8 bit of active Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x08)
board.WriteI2C(Ser_addr,0x67,0x05) #Least 4 bit AV + Most 4 bit AH
board.WriteI2C(Ser_addr,0x66,0x09)
board.WriteI2C(Ser_addr,0x67,0x30) #Most 8 bit of active Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x0A)
board.WriteI2C(Ser_addr,0x67,0x28) #Horizontal Sync Width
board.WriteI2C(Ser_addr,0x66,0x0B)
board.WriteI2C(Ser_addr,0x67,0x05) #Vertical Sync Width
board.WriteI2C(Ser_addr,0x66,0x0C)
board.WriteI2C(Ser_addr,0x67,0xDC) #Horizontal back porch
board.WriteI2C(Ser_addr,0x66,0x0D)
board.WriteI2C(Ser_addr,0x67,0x14) #Vertical back porch

#Setting up External Timing with External Clock
board.WriteI2C(Ser_addr,0x65,0x00) #using External Timing/CLK
board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars

Regards,
Fadi A.

Hi Fadi,

I have identified the reason why external timing fails on the UB947 side. The clock input has not been placed with a 100-ohm resistor. UB948 can be locked to UB947 and is capable of outputting the internal pattern with the external clock.The display shows OK while using external timing and internal pattern. However, a new issue has emerged on the UB947 side. When I modify the mode on UB947 using external timing and data (reg 0x65 = 0x00, by default), the display shows flicker (flashing). It appears that the external LVDS control signals (DE/VS/HS) are not aligne with internal pattern.  Is there any specific format for the LVDS input ?  

Regards,

Kexiang

Hey Kexiang,

Kexiang Fu said:

It appears that the external LVDS control signals (DE/VS/HS) are not aligne with internal pattern.  Is there any specific format for the LVDS input ?  

No, you shouldn't need to change any settings or format between internal pattern and external CLK mode (0x65 = 0xC0) and external timing/CLK mode (0x65= 0x0) except for register 0x65 value.

So if you are not seeing an issue with internal timing and external clock mode and seeing HS/VS/DE issue with external timing/CLK mode then this points to a timing issue coming from the video source.

The only thing you can change is MAPSEL from Mode_Sel1 pin strap or register override. You can also check the filter enable setting in register 0x03 which should be enabled by default.

However, in MAPSEL issues you will have some discoloration, etc. but in your case with flickering screen/flashing this seems to be a more of a hardware implementation for the data lanes as well to ensure 100 ohm is applied to all lanes and make sure the SoC or video source has a stable video output. 

MAPSEL register setting

HS/VS/DE Filter settings

Regards,
Fadi A.