DP83867IS: Compliance Test

Hi Ishiwata,

May I ask what speed are you testing the return loss?

• 1000Mbps, 100Mbps, or 10Mbps

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Regards,

Hillman Lin

Hi Hillman,

Thank you for your reply.
It will be 100Base, so it will be 100Mbps.

Best Regards,
Ishiwata

Hi Hillman,

Could you please explain more about Ethernet compliance testing?

A customer made a correction.

(1) For return loss, it is 100Mbps. Do both the Transmitter and Receiver need to be set to Test Mode 5?

(2) For twisted pair models, it is 10Mbps. Which twisted pair model should I set it to? Do I need to run both?

Best Regards,
Ishiwata

Hi Hillman,

Thank you for your answer.

I have an additional question.

Is Restart PHY necessary to run a compliance test?

Best Regards,
Ishiwata

Hi Shuji,

Reset is recommended but not required to run the compliance test.

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Regards,

Hillman Lin

Hi Hillman,

Thank you for your answer.

I performed an Ethernet compliance test, but the following items failed.

1000 Base-T, Point F Template Test (w/ Disturbing Signal)
1000 Base-T, Point H Template Test (w/ Disturbing Signal
1000 Base-T, Transmitter Distortion (w/ Disturbing Signal)

What are some possible reasons?

Best Regards,
Ishiwata

Hi Ishiwata,

The compliance test failure may cause by the schematic and layout of the customer's board

If possible, could you share the schematic around the magnetic side? Here is the schematic checklist we have for DP83867.

• 2110.DP83867_Schematic_Design_Review_Checklist (1).xlsx

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Regards,

Hillman lin

Hi Hillman,

Thank you for your support.

I have asked the customer to fill out a checklist and provide a circuit diagram.
I have sent the checklist and circuit diagram in a private message, so please check it.

Best Regards,
Ishiwata

Hi Ishiwata,

I see that customer is putting multiple pull down capacitors on the MDI lines.

If customer remove those capacitors on the MDI lines, Is customer seeing a better compliance performance?

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Regards,

Hillman Lin

Hi Hillman,

Thank you for your support.

The pull-down capacitor on the MDI line will not be implemented.

It is written in Japanese, so it is understandable that you cannot understand it.

Are there any other possible reasons?

Best Regards,
Ishiwata

Hi Ishiwata,

If those capacitors is not populated, the schematic looks fine to me.

The next step I would focus on the layout. If possible, could customer refer to the following layout checklist specially the layout on the MDI lines?

• 1563.Industrial_PHY_Layout Review Checklist.xlsx

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Thank you,

Hillman Lin

Hi Hillman,

Thank you for your support.
I will provide the layout checklist to the customer.

Additional information has been received from the customer.

Depending on the register settings, the compliance test may or may not pass.
If the register settings are in the old document (snla239b), it will pass.
If the register settings are in the new document (snla239c), it will fail.

The settings are as follows.

The waveforms differ depending on the register settings.
Q1: Why are the waveforms different?
Q2: Which settings are correct for compliance testing?

Best Regards,
Ishiwata

Hi Ishiwata-san,

Sorry for the delay. I discuss it with the team internally.

Yes, you are correct. We are missing one more script on for the new appnote.

Please refer to the following FAQ for more detail:

• https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1367619/faq-dp83867e-1000base-t-ethernet-compliance-register-script

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Sincerely,

Hillman Lin