DP83TG720S-Q1: SMI

Hello,

Can you explain the meaning of MAC changing direction of MDIO signal? I am not seeing it on the arrows from waveform sent. What do arrows signify in waveform? 

Can you elaborate on abnormal glitches please?

Regards,

Avtar

In the SMI protocol, a read operation means that in the first half, the MAC sends the register address of the PHY, and in the second half, the PHY sends the information. There are glitches on the MDIO when the PHY sends the information. The arrows indicate where the glitches occur.

Thank you for clarifying, I understand now. Does this cause  issues in register read/write operation?

Currently, this issue isn't causing any problems because the MAC samples the information sent by the PHY on the falling edge of the MDC, while the abnormal spike appears on the rising edge of the MDC. However, the cause of this issue is unclear, and there is uncertainty about whether it might appear on the falling edge in the future, which could lead to sampling errors.

Hello,

I will have to discuss this with my internal team and get back to you as this is an unknown phenomenon. 

Regards,

Avtar

Thanks a lot.

There seems to be some noise on the MDIO line on the rising edge, can you please send the schematic and layout for the MDIO area so we can check for any causes?

Regards,

Avtar

The MDIO is connected directly to the MAC through a pull-up resistor, and the power supply for the pull-up is stable according to the test waveform. There are no high-speed signals near the MDIO trace, so it doesn't seem to be interfered with by surrounding traces. This is because the abnormal glitch only appears in the second half of the read operation, while the rest of the time it is a stable pulse waveform or idle high state.

• what pullup resistor is used and what tolerance?
• I will review this layout picture with my internal team and get back to you.

We are using a 4.7K resistor with 1% precision for consistency in our materials.

I have reviewed the layout with internal team and there are no blatant issues seen, has this phenomenon ever interfered with MDC/MDIO communication reading or writing? 

At present, since the glitch occurs on the rising edge of the clock, it doesn't seem to cause any communication issues. However, since the mechanism behind this problem is unclear, I am concerned about the potential risks that may arise in the future.

From internal team as long as sampling occurs at falling edge, there should be no risks in communication or register access.