• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 316 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDP1204: Problem with LV_DDC_SDA not being able to hold the 'L' level of ACK data

Masashi Mineda
Expert 1155 points
Part Number: TDP1204

Tool/software:

Dear Sirs and Madams,

We are using a TDC1204 for level shifting between the GPU and the HDMI.

The SDA and SCL of HV_DDC are pulled up with 1.8k ohms at 5V.


The usage is as shown in the Simple Schematic, but there is a problem with the operation of the DDC level shifter.

HV_DDC_SDA is receiving ACK correctly.

ACK cannot maintain the 'L' level on LV_DDC_SDA after passing through the DDC buffer inside the TDP1204.

There was a similar issue on the E2E website, but the cause of the issue and specific solutions were not described.

TDP0604: Regarding the operation of the DDC level shifter when there is an internal pull-up/pull-down (which the master device has) on the LV_DDC_SDA/SCL side. and about the solution. - Interface forum - Interface - TI E2E support forums

Regards,

MM

  • +1
    TI__Mastermind 38150 points

    Hey,

    The reason we see this bump on the LV side is due to the hysteresis and thresholds of the DDC buffer. 

    In the case of the ACK. The data is being sent from the slave to the master HV_DDC -> LV-DDC. 

    When HV side falls first and goes below 1.6-V, a CMOS hysteresis input buffer detects the falling edge, turns on the LV driver, and pulls LV down to approximately VLVOL = 0.16 × VIO. The LV side pulldown is not enabled unless the LV voltage goes below VILC.

    Assuming a 3.3V VIO:

    VLVOL = 0.16 * VIO = 0.528V

    VILC = 0.08 * VIO = 0.2634.

    The issue you are running into is that the low level for the LV side is not less than VILC, so the LV side pulldown in not enabled. This results in the internal pullup raising the voltage. Try to keep the low level of the LV_DDC communication below the VILC value.

  • 0 in reply to Vishesh Pithadiya
    Expert 1155 points

    Hello Vishesh,

    When we checked the customer's configuration, we found that there was a 2.2kΩ pull-up resistor on the LV side of the TDP1204.

    It was connected in parallel with the 10kΩ built in TDP1204, resulting in a strong pull-up of approximately 1.8kΩ, and I found that I could not drive it to the 'L' level.

    I am sorry to have caused trouble.

    Regards,

    MM

  • 0 in reply to Masashi Mineda
    TI__Mastermind 38150 points

    No worries, glad we got it figured out!