Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 33 subscribers
  • Views 224 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH1218: 12G-SDI Video failure

Gaurav Agrawal
Intellectual 670 points
Part Number: LMH1218
Other Parts Discussed in Thread: LMH1219, USB2ANY

Tool/software:

Hello,

We are using LMH1218 OUT0 interface (75 Ohms) to output 4K/12G-SDI video to an Eizo Monitor. The data interface is from Ultrascale FPGA with GTX rated at 12.5 Gbps.

However, we are able to output only 6G rates, and the 12G signal appears momentarily as "Signal error", and then permanently as "No Signal" on the monitor.

1) The initialization steps shown in the datasheet are followed, but there is no difference in operation with or without it.

2) The connector used is 75 Ohm HD-BNC series from Samtec, and the HDBNC-BNC cable used is only 1.5 meters.

2) The CDR always shows locked - can we assume that the FPGA interface is working OK?

3) If the above is true, it seems the only setting for the OUT0 driver is OUT0_VOD, without any de-emphasis settings. Is that correct?

Regards

Gaurav

  • 0
    TI__Mastermind 24032 points

    Hi Gaurav,

    1. If CDR is always locked, this indicates that FPGA is outputting a data rate that LMH1218 can lock to.  You can confirm that this is 12G SDI by following the 4.2.11 "Lock Data Rate Indication" in the LMH1218 Programming Guide.
    2. Can you read the horizontal and vertical eye opening values from the LMH1218 internal eye monitor and share these with us?  You can use the sequence contained in 4.2.13 "Read Horizontal and Vertical Eye Opening" in the LMH1218 Programming Guide.
    3. What is the insertion loss from FPGA to LMH1218?  What CTLE setting are you using on the LMH1218?
    4. What sort of configuration are you doing on the LMH1218?
    5. Are you able to check the SDI output on a video analyzer or scope?  Do you have an alternative monitor you can check?
    6. Yes, VOD is the primary configurable parameter for TX.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Intellectual 670 points

    Hi Drew,

    Thank you for the quick reply. Here are our responses:

    1) Yes, its confirmed 11.88Gbps, register reads out 000'b.

    2) HEO is 53'd (0.82UI) and VEO is 108'd (337mV) which looks sufficient. We still increased the GTX swing in FPGA, and achieved a max VEO of 132'd (412mV). But result remains the same.

    3) At max GTX setting, the FPGA supposedly gives out 1080mV diff swing, which is received as 412mV inside LMH1218.

    CTLE setting is unchanged (Default 0x80).

    4) IN0 gets the input from FPGA, which goes out on OUT0 75Ohms output. We follow the initialization sequence recommended in prog guide.

    5) Sorry, we dont have any of these for 12G rates.

    6) We tried maximizing Vod but result remains the same. CDR lock and eye remains stable, but there is no video on monitor.

    We also have the receiver IC LMH1219 close-by on the board, with a similar BNC and FR4 trace/coupling cap arrangement as LMH1218. It works fine, we can receive 4K 12G-SDI video from an external camera. We tried to do a local loop from LMH1218 BNC output to LMH1219 BNC input, and LMH1219 CDR doesn't lock anymore.

    So problem somehow seems located on transmission output of LMH1218.

    Please let us know if anything else can be tried.

    Regards

    Gaurav

  • 0 in reply to Gaurav Agrawal
    TI__Mastermind 24032 points

    Hi Gaurav,

    CTLE of 0x80 is pretty high.  What's the estimated insertion loss between your FPGA and LMH1218?  Or if insertion loss is unknown, how long is the trace?

    Given that CTLE 0x80 is pretty high, as an experiment, could you try CTLE 0x00?

    Also, are you configuring the device via I2C?  If so, might it be possible to connect a USB2ANY to the I2C bus and use the LMH1218 SigCon Architect GUI profile for device configuration?  This would allow us to ensure that you're working with known good configuration and would also easily allow you to dump registers and share them with us.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Intellectual 670 points

    Hi Drew,

    Our differential trace length from FPGA to LMH1218 is around 2.7". We will try out CTLE 0x00 and let you know. But shouldn't CTLE be already ok as the eye readings are good?

    The 75 ohm track length from OUT0 to BNC is 0.5" including the coupling cap of 4.7uF.

    We configure device over SPI. If you need any register dumps, please let me know. USB2ANY will need to be procured, and that may take some time.

    Regards

    Gaurav

  • 0 in reply to Gaurav Agrawal
    TI__Mastermind 21250 points

    Hi Gaurav,

    Drew is currently out of office. He can get back to you later this week.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Mastermind 24032 points

    Hi Gaurav,

    The eye readings you shared do seem good, but the CTLE value you shared seems really high for 2.7" trace.  I think it's worth trying CTLE = 0x00 and checking performance and eye in this case to ensure that the signal is not getting over-equalized.

    If you can share a register dump of the device, that would be helpful.

    Do you have any evidence supporting that data coming from FPGA is correct?  Right now we are assuming that somehow bit errors are occurring on either LMH1218 RX or TX.  The fact that you can't get lock on LMH1219 seems to suggest some sort of issue with LMH1218 TX.

    Also, is this a known good cable?  Have you tried a different cable?

    Thanks,

    Drew