Tool/software:
For DP83822, there is a guidance where AVD and VDDIO must not exceed 0.3V prior to complete supply ramp, with an additional footnote suggesting AVD to ramp up after VDDIO to avoid false detection of VDDIO. False detection may lead to non-operational performance from the device, such as no link up. If such a case is happening, it may be helpful to read register 0x421 to indicate what supply level the PHY is operating at and compare to intended levels. If a level is mis-detected, a way to bypass and rectify would be adjusting Reg 0x41F accordingly. Please note these registers are extended registers and thus will require 4-step process to read and write per datasheet.