DS100DF410: How it works well when CDR is unlocked

Hi Masaki,

1. Can you share the values of channel register 0x09 and 0x1E? This determines the output when CDR is locked/unlocked. With default settings, output is muted when CDR is unlocked and output is retimed data when CDR is locked.

2. Are you asking about raw data output when CDR is unlocked? With this setting, the signal will bypass the CDR but pass through other equalization and driver functional blocks.

Best,

Lucas

Hi Lucas,

Thank you for reply.

１．We reply as below, we set as overriding and retimed data, then CDR is kept unlocked.

         0x9        Channel 3_0x09 18

         0x1E      Channel 3_0x1E 29

2. Yes, that's right. you say, the signal will pass through other equalization and driver functional blocks,

    so, we want to know the concrete setting,  "other equalization and driver functional blocks"

     (but we have already checked Rx EQ/DFE and Tx DEM/PRBS Generator)

Best,

Masaki

Hi Masaki,

Lucas is out on travel this week, but Drew from my team should be able to get back to you.

Regards,

Rodrigo Natal 

HSSC Applications Manager

Hi Drew,

1. OK, we understood that "raw data" setting is normally recommended, but inour system, something abnormal happenned.

     In our system,  when CDR is unlocked,

     in "raw data" setting, the signal is worse than when DS100DF410 is not implemented.

     in "retimed data" setting, the signal is much better than when DS100DF410 is not implemented.

     So, we want to know what kind of processes are used when "retimed data" setting and CDR is unlocked. 

2. thank you for reply. please make sure 2 things below;

     --we understood that there are no other settings except for CTLE, DFE and tx de-emphasis settings, when it's unlocked, is it right? 

    --in SigConArchitect, we just click the setting in "High level Page > Tx DEM, or Rx EQ/DEM" and click  "High level Page > Apply to channel", could you tell us if these process is not enough?

Best,

Masaki

Hi Masaki,

Masaki Tsuji said:

1. OK, we understood that "raw data" setting is normally recommended, but inour system, something abnormal happenned.

     In our system,  when CDR is unlocked,

     in "raw data" setting, the signal is worse than when DS100DF410 is not implemented.

     in "retimed data" setting, the signal is much better than when DS100DF410 is not implemented.

     So, we want to know what kind of processes are used when "retimed data" setting and CDR is unlocked. 

It is a bit surprising that you're seeing better signal in "retimed data" setting than "raw data" setting when CDR is unlocked.  When CDR is unlocked, it's not clear to me what "retimed data" output will be.

Are you able to share a block diagram of your test setup as well as your test data rate and any device configuration details?

Masaki Tsuji said:

2. thank you for reply. please make sure 2 things below;

     --we understood that there are no other settings except for CTLE, DFE and tx de-emphasis settings, when it's unlocked, is it right? 

    --in SigConArchitect, we just click the setting in "High level Page > Tx DEM, or Rx EQ/DEM" and click  "High level Page > Apply to channel", could you tell us if these process is not enough?

You may need to manually set CTLE.  I can follow up with instructions on this later today.

Thanks,

Drew

Hi Masaki,

Please see the "Set CTLE Boost Value" section of the 10G retimer programming guide in order to manually set CTLE value.

Thanks,
Drew

Hi Drew,

1. we attached the simple test ssytem below,

we want to know the difference of process between "raw data" and "retimed data" when CDR is unlocked by overriding.

2. thank you, we're wainting the instruction.

Hi Masaki,

Thanks for the block diagram.  Apologies if I'm missing this, but by default, DS100DF410 is configured to lock to 10.3125 Gbps data.  How do you know that you aren't getting CDR lock in this configuration?  Do you have any custom configuration specific to inhibiting CDR lock?

Thanks,

Drew

Hi Drew,

We can know if the CDR is locked nor not by checking the GUI of SigConArchitect.

like the yellow highlights in the picture belw.

Hi Masaki,

Thanks for clarifying.  This behavior is a bit surprising.  Please let me check it out in lab and I will get back to you.

Thanks,

Drew