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DP83640: How to configure RX_SFD_GPIO to receive pulses from GPIO12 (CLOCK_OUT)?

mc b
Prodigy 165 points
Part Number: DP83640


Tool/software:

Hello ,

 I am currently trying to configure the DP83640's RX_SFD_GPIO functionality to utilize GPIO12 (CLOCK_OUT) for pulse reception. To begin, I've disabled the clock output by setting the CLK_OUT_DIS bit to 0 in the PHYCR2 register.

I proceeded by navigating to page 6 after changing the PAGESEL value to 6. Post this, I configured the RX_SFD_GPIO to be on GPIO12 by assigning a value of 12 to the PTP_SFDCFG register (address 0x19). Additionally, I ensured that the PTP_COC (address 0x14) is set to 0.

The setup is intended to capture events when sending Ethernet packets and PTPv2 synchronization messages. Despite following these steps, there is no observable level change on the DP83640's GPIO12 (CLOCK_OUT) pin.

Q-1) Am I missing any additional configurations or specific settings? Any insights into enabling pulse detection on the CLOCK_OUT pin would be appreciated.

Q-2): Does the IEEE 1588 Start Frame Delimiter (SFD) feature activate for any Ethernet frame, or is it specific to valid Ethernet frames containing PTP messages? My assumption is that the RX SFD signal is generated for all Ethernet frames, because how would the system be able to discern if the frame contains PTP data at the very beginning of the frame?

Thanks

  • +1
    TI__Mastermind 25048 points

    Hi,

    Q1) This configuration looks correct, but I will double-check if there is anything missing. You are probing the GPIO during packet transmission?

    Q2) Your assumption is correct, SFD will be present on every frame with PTP enabled.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 165 points

    yes i am probing the gpio, and i have also solved the issue by adding this setting ;

     MDIOPhyRegWrite(MDIO_BASE, PHY_ADDR, PTP_CTL, 4);
     i suspected from bitfield's naming and i set PTP_ENABLE bit of the PTP_CTL , then i was able to observe SFD pin triggered properly. 
    but description is confusing in the datasheet ;
    "Enable PTP Clock: Setting this bit will enable the PTP Clock. Reading this bit will return the current enabled value. Writing a 0 to this bit will have no effect."
    dp83640 has internal ptp timestamping clock too , i was thinking this enables that clock and timestamping stuff, but it seems it also controls 1588SDF functionality too.  Without enabling this sfd pin is always low.  If this is true , i think better to update the datasheet. 
  • +1 in reply to mc b
    TI__Mastermind 25048 points

    Glad you found the working configuration.

    The timestamping engine used to trigger GPIOs on SFD receive is dependent on this PTP_ENABLE bit. I agree the naming of the description is misleading with "Enable PTP Clock", I have noted to clarify this in next datasheet revision.

    Thank you,

    Evan