DP83867E: Power sequencing for external oscillator

Michal Zamazal6

Part Number: DP83867E

Tool/software:

Hi, In the datasheet time diagram the XI 25 MHz clock signal is present before VDD power up. Is it possible the following power up power sequence:

1. VDDIO 3.3 V

2. VDDOSC 1.8 V - startup of the connected 25 MHz oscillator

some delay, how many cycles of the 25 MHz clock?

3. VDDA2P5+VDDA1P8+VDDA1P0

or there is also required the clock shall be present before VDDIO (3.3 V) power up?

Thanks.

over 1 year ago

0 Evan Mayhew over 1 year ago

TI__Mastermind 24998 points

Hi Michal,

Clock shall be present at or before power rails begin ramping. Otherwise, PHY's state machine cannot proceed with power-up sequence.

Is this feasible for your design?

Thank you,

Evan

0 Michal Zamazal6 over 1 year ago in reply to Evan Mayhew

Prodigy 110 points

Hi Evan,

Thanks. So it means there isn't possible to activate the clock signal later (in several miliseconds) after 3.3 V VDDIO is up also when the PHY is held in reset state? So it would require additional switch enabled with delay for VDDIO in our design.

0 Evan Mayhew over 1 year ago in reply to Michal Zamazal6

TI__Mastermind 24998 points

Hi Michal,

That is correct, clock must be available before power rails begin ramping.

If clock is not available, it's recommended to hold RESET_N low and release it 100us after clock is stable.

Thank you,

Evan

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DP83867E: Power sequencing for external oscillator