Tool/software:
Hi,
A customer has inquired about the Reset function of the DP83825I. I would appreciate it if you could give me some advice.
[Symptoms]
In the case where the CPU on the HOST (MAC) side is reset and the CLK stops, then the PHY is reset and restarted,
If the timing is as shown in waveform ① below, repeated restarts will result in the device not linking up properly.
The frequency varies depending on the individual, but in some cases the link-up will be successful and in other cases it will not.
RESET is input before CLK input.
The RESET width is 1 ms, which is greater than the specified 0.025 ms, so there is no problem.
The RESET→MDC timing is 8 ms, which is greater than the specified 2 ms, so there is no problem.
*CLK:XI/50MHzIN, RESET:RST_N
[Questions]
As shown in waveform ①, if CLK is not in an input state when RESET = L is input, is it possible that the IC will not start up normally and link-up will fail due to its specifications?
・Is the RESET input procedure as shown in waveform ② correct?
※It seems like an improvement for waveform ②, but there are cases where link-up is possible with waveform ①,
so It would be appreciated if there was a design basis for this, so please confirm.
The OS driver has been improved to match the timing of waveform ② below.
As of August 22nd, link-up was working normally and the symptoms appear to have improved.
The input is in the order of CLK→RESET→MDC.
The RESET width is 1 ms, which is greater than the specified 0.025 ms, so there is no problem.
The RESET→MDC timing is 8 ms, which is greater than the specified 2 ms, so there is no problem.
*CLK:XI/50MHzIN, RESET:RST_N
Best regards,
Hiroshi
