Tool/software:
HI,
the "serial rate" refers to the data rate per lane, not the clock speed？
If the serial rate is 400 Mbps per lane, the clock speed
- The clock speed would be 400 Mbps / 2 = 200 MHz.
The UB954’s receiver requires that the CSI-2 TX output clk frequency must be below 296 MHz. ?
1.How can I configure the UB954 to ensure that the CSI-2 TX output clk frequency remains below 296 MHz?
2.How is the MIPI frequency set for a UB954 pattern with a resolution of 1920x1080, RGB, and 30fps?
How can i configure pattern mipi clk below 296Mhz?
{0x32, 0x01}, /* Select Port0 registers */
{0xB0, 0x00}, /* Indirect Pattern Gen Registers */
{0xB1, 0x01}, /* PGEN_CTL */
{0xB2, 0x01},
{0xB1, 0x02}, /* PGEN_CFG */
{0xB2, 0x33},
{0xB1, 0x03}, /* PGEN_CSI_DI */
{0xB2, 0x24},
{0xB1, 0x04}, /* PGEN_LINE_SIZE1 */
{0xB2, 0x16},
{0xB1, 0x05}, /* PGEN_LINE_SIZE0 */
{0xB2, 0x80},
{0xB1, 0x06}, /* PGEN_BAR_SIZE1 */
{0xB2, 0x02},
{0xB1, 0x07}, /* PGEN_BAR_SIZE0 */
{0xB2, 0xD0},
{0xB1, 0x08}, /* PGEN_ACT_LPF1 */
{0xB2, 0x04},
{0xB1, 0x09}, /* PGEN_ACT_LPF0 */
{0xB2, 0x38},
{0xB1, 0x0A}, /* PGEN_TOT_LPF1 */
{0xB2, 0x07},
{0xB1, 0x0B}, /* PGEN_TOT_LPF0 */
{0xB2, 0x08},
{0xB1, 0x0C}, /* PGEN_LINE_PD1 */
{0xB2, 0x06},
{0xB1, 0x0D}, /* PGEN_LINE_PD0 */
{0xB2, 0x33},
{0xB1, 0x0E}, /* PGEN_VBP */
{0xB2, 0x28},
{0xB1, 0x0F}, /* PGEN_VFP */
{0xB2, 0x0F},
{0x33, 0x03}, /* CSI0 enable */
3.How do you set the frame rate to 60fps
