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DS250DF810: DS250DF810 Vod in RAW mode

Maksim Zaitsev
Prodigy 10 points
Part Number: DS250DF810
Other Parts Discussed in Thread: DS250DF230, TDP2004

Tool/software:

Hello,

What the value of VOD on TX side in RAW mode. Is it defined just by RX's CTLE/VGA or  it is constant and defined by some other reg. Maybe the info is in datasheet but i am not good enouph in analog modules to find it  in inderect way.

Best regards,

Maksim

  • 0
    TI__Mastermind 22042 points

    Hi Maksim,

    In RAW mode, there is not much direct control over the TX VOD.  I believe the signal goes through a limiting stage, so I wouldn't expect VGA to have a huge impact.

    I have seen around 600-700 mVppd TX amplitude in RAW mode.

    Here is an eye capture I have taken of RAW mode in the past.

    6.75" ISI Board Trace: 6 dB insertion loss at 12.89 GHz

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hello, Drew.


    My main question may be stupid but i did not find any characteristic output channels (Vod) for RAW mode: Is TX-Vop value a constant in RAW mode? What i see now is while changing at least voltage swing on the input from 600mV to 1000mV i cannot see the changes in voltage swing on the output. So it seems the Vod on the output is a constant in the RAW mode or  it must be defently the fuction of input and i did not configure RAW mode properly?

    Best regards,

    Maksim

  • 0 in reply to Maksim Zaitsev
    TI__Mastermind 22042 points

    Hi Maksim,

    You main question is not stupid; thanks for clarifying your question and sharing your observation.  Since DS250DF810 has a limiting stage in RAW mode, we will not expect input swing to have an impact on output swing as output swing will be "limited" to a max value.  In other words, RAW mode is a non-linear signal chain.

    The DS250DF810 does not have a setting that directly controls RAW mode VOD.  Looking at our 25G retimer programming guide (SNLU182), there is a section on adjusting RAW VOD swing, but is targeted at DS250DF230.  The DS250DF810 does not have the RAW_TX_SWING control bit (ch_reg_0x0D[0]) found on DS250DF230.

    You could try adjusting the RPH register (ch_reg_0x1A[7:6]).  The default value is 1.  The RPH register impacts bias currents for the entire device.  You could try setting this to 2 or 3 and see if this increases RAW swing.  Note that this is expected to increase device power consumption.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hello, Dreq.

    Thank you. I've tried playing with RPH register (ch_reg_0x1A[7:6]) and could change Vod slightly. But it is not what we want. It seems that the chip is not suitable for us because we wanted to use it to be compatible with Display Port 2.1, sourcing from FPGA.

    So more direct questions:

    1. Could you confirm that Vod is constant in RAW mode and it is not depended on input signal (if it is detected)?
    2. Could DS250DF810 support Display Port 2.1 frequencies ( 1.62, 2.7, 5.4, 8.1, 10, 13.5, 20) in retimer mode?

          According to the table 5 of datasheet, it is not, except 5.4, but i am asking just in case.

    1. I have tried to get CDR locked with 5.4Gbit using steps from 7.7.1 chapter of UG but no luck. What could I missed? To me 5.4 is only bitrate which should be supported by the chip.
    2. If no chances with the current chip. What chip do you recommend for replacement candidate to be DP 2.1 compatible. Retimer is desirable but rediriver is also ok.

    Best regards,

    Maksim

  • 0 in reply to Maksim Zaitsev
    TI__Guru**** 154921 points

    Hi Maksim

    Due to the US Labor Day holiday, the response to your question may be delayed. We will look into your question when we return tomorrow, Sept 3rd. Sorry for the wait and any inconvenience it may cause.

    Thanks,

    David

  • 0 in reply to David (ASIC) Liu
    TI__Mastermind 22042 points

    Hi Maksim,

    1. DS250DF810 VOD is basically constant in RAW mode due to high gain limiting amplifier.

    2. DS250DF810 supports locking to the rates in table 5.  It cannot lock to all the rates you listed.

    3. I expect the device to support 5.4 Gbps, 10 Gbps, and 20 Gbps in retime mode.  Section 7.7.1 is the right section to reference.  A couple things to note:

    • I believe there is a gap in the programming guide.  Note that there are two formulas depending on whether the data rate is less than or greater than 13.9 Gbps.  However, these formulas just scale based on whether data is div 1 or div 2.  For 5.4 Gbps, this is div 4.  Please try using full rate formula with full data rate (5.4*4 Gbps).
      • 0x60 = 0x00
      • 0x61 = 0xB6
      • 0x18[6:4] = 2
    • Also, I'm not too familiar with DP, but I'm wondering if there is any auto-negotiation.  If there's auto-negotiation, is there any possibility that your 5.4 Gbps source is sending 5.4 Gbps without first handling auto-negotiation?

    4. TI has a TDP2004 redriver.  Since this is specific to DP, I would expect this to work better.

    Also, I recall that HDMI/DP may have some specific DC-coupling requirements.  Have you taken this into consideration when selecting DS250DF810?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    TI__Guru**** 154921 points

    Maksim

    DS250DF810 is not a dedicated DP re-timer, its TX VOD and Pre-emphasis may not be compliant to the DP specification.

    TDP2004 is a linear re-driver. If you have a source that is DP compliant and if its TX output is within the TDP2004 linear range, then TDP2004 will faithfully re-produce that output at its TX output.

    Thanks

    David

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hi,

    Thank you. I was able to get CDR locked for 5.4 Gbit (div=4, 4*5.4Gbits), 2.7 (div=8, 8*2.7Gbits) and even 1.62 (div=16, 16*1.62Gbits). But no chances for 8.1G,10G,13.5G,20G because, as I understand with any supported dividers(1,2,4,8,16) those freqs do not fit into 20.2752 - 25.8 range. Or maybe there are undocumented possibility to define div=3, isn't there? Also is there possibiblity to change CAL_CLK generator? As i understand from datasheet it must be only 25MHz, but is that not possible at all or it would degrate some characteristics?

    Sorry, for asking things, even though it is quite understandable that we should use another chip but I would like to get the maximum from DS250DF810, maybe with some degradation of a signal. It would help us anyway.

    About DC-coupling requirements: from spec there must be AC-coupling and yes 220pF is complained to spec as well

    Tnank you for TPD2004 link. You have just confirmed my desire to look at the chip and we have already ordered EVM.

     

    Best regards,

    Maksim

  • 0 in reply to Maksim Zaitsev
    TI__Mastermind 22042 points

    Hi Maksim,

    Glad to hear you were able to progress with 5.4 Gbps and even subrates of this.  Also glad to hear that you're looking into TDP2004.

    Unfortunately there is not an undocumented possibility of divide by 3.  For this device, the supported rates will be 2^n of the full rate.

    In theory, it might be possible to use a different CAL_CLK.  Our DS250DF230 supports 25 MHz and 30.72 MHz.  However, please note this has no impact on the data rates that the device can lock to.  The CAL_CLK is just used to roughly calibrate VCO frequency.  The full-rate lock range is bounded by VCO lower and upper rates.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Thank you Drew, David for the fast and informative supporting.