DS90UB962-Q1: No camera picture output

Part Number: DS90UB962-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Tool/software:

We have appled the parameters as follows:

0x4C,0x01, //RX Port0 write enable
0x58,0x5E, //I2C pass-through, BCC 50Mbps
0x07,0xFF, // disable BCC watchdog
0x09,0x81,
0x5C,0xb0, //933 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x12, //RX Port1 write enable
0x58,0x5E, //I2C pass-through, BCC 50Mbps
0x07,0xFF, // disable BCC watchdog
0x09,0x81,
0x5C,0xb0, //933 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x24, //RX Port2 write enable
0x58,0x5E, //I2C pass-through, BCC 50Mbps
0x07,0xFF, // disable BCC watchdog
0x09,0x81,
0x5C,0xb0, //933 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x38, //RX Port3 write enable
0x58,0x5E, //I2C pass-through, BCC 50Mbps
0x07,0xFF, // disable BCC watchdog
0x09,0x81,
0x5C,0xb0, //933 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x5E,0xDA, //GW5200 physical address
0x66,0xDA, //GW5200 alias address
0x5F,0xD8, //GW5200 failsafe address
0x67,0xD8, //GW5200 failsafe address
0x6D,0x7C, //CSI setting
0x6E,0xA8, //BC_GPIO0=0, GC_GPIO1=Fsync
0x70,0x1E, //vc0,YUV422
0x72,0xE4, //vc0
0x7C,0xC1,

0x32,0x01,
0x33,0x03,// #CSI OUT ENABLE ,enable continuous clock
0x20,0xC0,// #CSI FORWARDING PORT0,1

//frame sync settings, For 25-Mbps backchannel operation,
//the frame period is 1200 ns (30 bits x 40 ns/bit).
//30fps, 33333333/1200=27777=0x6C81
//0x6E,0xA0,
//0x19,0x0C,//FS_HIGH_TIME_1
//0x1A,0x81,//FS_HIGH_TIME_0
//0x1B,0x60,//FS_LOW_TIME_1
//0x1C,0x00,//FS_LOW_TIME_0
//0x18,0x01,//FrameSync Enable

//50fps
//frame sync settings, For 50-Mbps backchannel operation,
//the frame period is 600 ns (30 bits x 20 ns/bit).
//50fps, 20000000/600=33333=0x8235
0x6E,0xA0,
0x19,0x02,//FS_HIGH_TIME_1
0x1A,0x35,//FS_HIGH_TIME_0
0x1B,0x80,//FS_LOW_TIME_1
0x1C,0x00,//FS_LOW_TIME_0
0x18,0x01,//FrameSync Enable

then input a ntsc camera, but can not show the camera picture, and the MIPI has waveform.

The question is how we can check and investigate it?

  • Hi Robin,

    Thanks for this question. Could you confirm a few points below?

    1. I see that UB933 is noted in the script, however at other points BC is set to 50Mbps in 0x58. Could you confirm what the correct partner serializer here is? If UB933 is used we need to set the BC rate to 2.5Mbps
    2. Have you read any diagnostics here? A good starting point would be deserializer register 0x4D which will show lock status between ser/des
    3. If UB933 is used we will need to convert DVP video to CSI video, this should be added to the config script.
    4. Once streaming starts from the sensor, we should see the line length and line count in registers 0x73 - 0x76 of the deserializer. Do these registers read back active data at the FPD RX?
    5. In the schematic do you know what mode select is set to? the FPD RX mode may need to be overridden if not set correctly.

    Appreciate your help clarifying these points, let me know if there's anything I can clarify here.

    Best,

    Thomas

  • Hi Thomas,

    We use UB933,I think we need initialize UB933 by UB962, Can you give me some sample code to show how to initialize UB933? Thanks

  • Hi Robin,

    What is the mode select of the serializer you are using here? This will determine what needs to be overridden to link to UB933. Please see the below table from the UB962 datasheet, we're looking for which of these modes has been selected from the hardware side on the mode pin of UB962.

    Best,

    Thomas

  • Hi Thomas,

    The mode of UB962 is CSI-2 Mode, and the mode of UB933 is External Oscillator, the format of Image Sensor is YUV422 10BIT.

    Best Regards!

  • Hello Robin,

    You can't set the UB962 into CSI-2 Sync mode when pairing with the 933. In your case, you have to use the 962 in DVP RAW10 mode.

  • Hi Hamzeh,

    Can you tell me the deference between the mode No. 3 and No. 7 as follows:

    and which mode we should use?

    Best Regards!

  • Hi Thomas,

    We read the register 0x4D, the value is 0xC0, it means unlock between set/des, How we check this ?

  • Hi Robin,

    Can you tell me the deference between the mode No. 3 and No. 7 as follows:

    There is no differences. You can select any.

    and which mode we should use?

    You should be using the same mode on both, SER and DES. If using RAW10 on the SER, then select any of the two RAW10 modes on the DES.

    We read the register 0x4D, the value is 0xC0, it means unlock between set/des, How we check this ?

    0x4D = 0xC0 means your used port is RX3, and LOCK is low.

  • Hi Hamzeh,

    We use the combination of UB962 and UB933, we can not show camera until now. so we need confirm the Colorbar can show with UB962 first.

    Can you give us the register config script for generate ColorBar?

    Thanks very much!

  • Hi Robin,

    in order to be able to generate the Pattern code, I need your intended resolution, data type and frame rate. Alternatively, you can use our ALP to generate any pattern you want to the UB962.

    Also, if you can provide me with the registers dump from the UB962 for the right RX port, then I can review these for you and see what is going on.

  • Hi Hamzeh,

    You can use 720p, YUV422 10Bit and 30fps to generate the Pattern code.

    Thanks.

  • Hello Robin,

    here is an example script:

    board.WriteReg(0x33, 0x03)                
                                
    board.WriteReg(0xB0, 0x02)                # IA_AUTO_INC=1
    board.WriteReg(0xB1, 0x01)                # PGEN_CTL
                                
    board.WriteReg(0xB2, 0x01)                # PGEN_ENABLE=1
    board.WriteReg(0xB2, 0x35)                # PGEN_CFG
    board.WriteReg(0xB2, 0x1F)                # PGEN_CSI_DI
    board.WriteReg(0xB2, 0x0C)                # PGEN_LINE_SIZE1
    board.WriteReg(0xB2, 0x80)                # PGEN_LINE_SIZE0
    board.WriteReg(0xB2, 0x01)                # PGEN_BAR_SIZE1
    board.WriteReg(0xB2, 0x90)                # PGEN_BAR_SIZE0
    board.WriteReg(0xB2, 0x02)                # PGEN_ACT_LPF1
    board.WriteReg(0xB2, 0xD0)                # PGEN_ACT_LPF0
    board.WriteReg(0xB2, 0x03)                # PGEN_TOT_LPF1
    board.WriteReg(0xB2, 0x20)                # PGEN_TOT_LPF0
    board.WriteReg(0xB2, 0x10)                # PGEN_LINE_PD1
    board.WriteReg(0xB2, 0x47)                # PGEN_LINE_PD0
    board.WriteReg(0xB2, 0x0A)                # PGEN_VBP
    board.WriteReg(0xB2, 0x0A)                # PGEN_VFP
    board.WriteReg(0xB2, 0xAA)                # PGEN_COLOR0
    board.WriteReg(0xB2, 0x33)                # PGEN_COLOR1
    board.WriteReg(0xB2, 0xF0)                # PGEN_COLOR2
    board.WriteReg(0xB2, 0x7F)                # PGEN_COLOR3
    board.WriteReg(0xB2, 0x55)                # PGEN_COLOR4
    board.WriteReg(0xB2, 0xCC)                # PGEN_COLOR5
    board.WriteReg(0xB2, 0x0F)                # PGEN_COLOR6
    board.WriteReg(0xB2, 0x80)                # PGEN_COLOR7
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR8
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR9
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR10
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR11
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR12
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR13
    board.WriteReg(0xB2, 0x00)                # PGEN_COLOR14
    board.WriteReg(0xB2, 0x00)                # Reserved

  • Hi Hamzeh,

    We still cannot show Pattern mode with this script, as your mention, How should we dump the registers?

    Thanks!

  • Hi Robin,

    You need I2C access to the DES. You may use USB2ANY or any other programmer dongle to communicate with the DES.

    Once you have communication with the DES, you need to read the values of all the DES registers starting from 0x01 until 0xFF

  • Hi Hamzeh,

    We have dumped the DES registers from 0x01 to 0xFF under Pattern mode. Please help me check this:

    reg[0x0]:0x60
    reg[0x1]:0x0
    reg[0x2]:0x1e
    reg[0x3]:0x40
    reg[0x4]:0xd0
    reg[0x5]:0x1
    reg[0x6]:0x0
    reg[0x7]:0xfe
    reg[0x8]:0x1c
    reg[0x9]:0x10
    reg[0xa]:0x7a
    reg[0xb]:0x7a
    reg[0xc]:0xf
    reg[0xd]:0xb9
    reg[0xe]:0x1
    reg[0xf]:0xff
    reg[0x10]:0x0
    reg[0x11]:0x0
    reg[0x12]:0x0
    reg[0x13]:0x0
    reg[0x14]:0x0
    reg[0x15]:0x0
    reg[0x16]:0x0
    reg[0x17]:0x0
    reg[0x18]:0x0
    reg[0x19]:0x0
    reg[0x1a]:0x0
    reg[0x1b]:0x0
    reg[0x1c]:0x0
    reg[0x1d]:0x0
    reg[0x1e]:0x4
    reg[0x1f]:0x2
    reg[0x20]:0xf0
    reg[0x21]:0x3
    reg[0x22]:0x0
    reg[0x23]:0x0
    reg[0x24]:0x0
    reg[0x25]:0x0
    reg[0x26]:0x0
    reg[0x27]:0x0
    reg[0x28]:0x0
    reg[0x29]:0x0
    reg[0x2a]:0x0
    reg[0x2b]:0x0
    reg[0x2c]:0x0
    reg[0x2d]:0x0
    reg[0x2e]:0x0
    reg[0x2f]:0x0
    reg[0x30]:0x0
    reg[0x31]:0x0
    reg[0x32]:0x0
    reg[0x33]:0x0
    reg[0x34]:0x0
    reg[0x35]:0x0
    reg[0x36]:0x0
    reg[0x37]:0x0
    reg[0x38]:0x0
    reg[0x39]:0x0
    reg[0x3a]:0x0
    reg[0x3b]:0x0
    reg[0x3c]:0x0
    reg[0x3d]:0x0
    reg[0x3e]:0x0
    reg[0x3f]:0x0
    reg[0x40]:0x0
    reg[0x41]:0xa9
    reg[0x42]:0x71
    reg[0x43]:0x1
    reg[0x44]:0x0
    reg[0x45]:0x0
    reg[0x46]:0x20
    reg[0x47]:0x0
    reg[0x48]:0x0
    reg[0x49]:0x0
    reg[0x4a]:0x0
    reg[0x4b]:0x12
    reg[0x4c]:0x0
    reg[0x4d]:0x17
    reg[0x4e]:0xe5
    reg[0x4f]:0x29
    reg[0x50]:0xff
    reg[0x51]:0x0
    reg[0x52]:0x0
    reg[0x53]:0x0
    reg[0x54]:0x0
    reg[0x55]:0xff
    reg[0x56]:0xff
    reg[0x57]:0x0
    reg[0x58]:0x18
    reg[0x59]:0x0
    reg[0x5a]:0x0
    reg[0x5b]:0xba
    reg[0x5c]:0x0
    reg[0x5d]:0x0
    reg[0x5e]:0x0
    reg[0x5f]:0x0
    reg[0x60]:0x0
    reg[0x61]:0x0
    reg[0x62]:0x0
    reg[0x63]:0x0
    reg[0x64]:0x0
    reg[0x65]:0x0
    reg[0x66]:0x0
    reg[0x67]:0x0
    reg[0x68]:0x0
    reg[0x69]:0x0
    reg[0x6a]:0x0
    reg[0x6b]:0x0
    reg[0x6c]:0x0
    reg[0x6d]:0x7f
    reg[0x6e]:0x88
    reg[0x6f]:0x88
    reg[0x70]:0x2b
    reg[0x71]:0x2c
    reg[0x72]:0xe4
    reg[0x73]:0x2
    reg[0x74]:0xff
    reg[0x75]:0xa
    reg[0x76]:0x0
    reg[0x77]:0xc5
    reg[0x78]:0x0
    reg[0x79]:0x1
    reg[0x7a]:0x0
    reg[0x7b]:0x0
    reg[0x7c]:0x20
    reg[0x7d]:0x0
    reg[0x7e]:0x0
    reg[0x7f]:0x0
    reg[0x80]:0x0
    reg[0x81]:0x0
    reg[0x82]:0x0
    reg[0x83]:0x0
    reg[0x84]:0x0
    reg[0x85]:0x0
    reg[0x86]:0x0
    reg[0x87]:0x0
    reg[0x88]:0x0
    reg[0x89]:0x0
    reg[0x8a]:0x0
    reg[0x8b]:0x0
    reg[0x8c]:0x0
    reg[0x8d]:0x0
    reg[0x8e]:0x0
    reg[0x8f]:0x0
    reg[0x90]:0x0
    reg[0x91]:0x0
    reg[0x92]:0x0
    reg[0x93]:0x0
    reg[0x94]:0x0
    reg[0x95]:0x0
    reg[0x96]:0x0
    reg[0x97]:0x0
    reg[0x98]:0x0
    reg[0x99]:0x0
    reg[0x9a]:0x0
    reg[0x9b]:0x0
    reg[0x9c]:0x0
    reg[0x9d]:0x0
    reg[0x9e]:0x0
    reg[0x9f]:0x0
    reg[0xa0]:0x0
    reg[0xa1]:0x0
    reg[0xa2]:0x0
    reg[0xa3]:0x0
    reg[0xa4]:0x0
    reg[0xa5]:0x1b
    reg[0xa6]:0x0
    reg[0xa7]:0x0
    reg[0xa8]:0x0
    reg[0xa9]:0x0
    reg[0xaa]:0x0
    reg[0xab]:0x0
    reg[0xac]:0x0
    reg[0xad]:0x0
    reg[0xae]:0x0
    reg[0xaf]:0x0
    reg[0xb0]:0x2
    reg[0xb1]:0x20
    reg[0xb2]:0x0
    reg[0xb3]:0x8
    reg[0xb4]:0x25
    reg[0xb5]:0x0
    reg[0xb6]:0x18
    reg[0xb7]:0x0
    reg[0xb8]:0x8f
    reg[0xb9]:0x33
    reg[0xba]:0x83
    reg[0xbb]:0x74
    reg[0xbc]:0x80
    reg[0xbd]:0x0
    reg[0xbe]:0x0
    reg[0xbf]:0x0
    reg[0xc0]:0x0
    reg[0xc1]:0x0
    reg[0xc2]:0x0
    reg[0xc3]:0x0
    reg[0xc4]:0x0
    reg[0xc5]:0x0
    reg[0xc6]:0x0
    reg[0xc7]:0x0
    reg[0xc8]:0x0
    reg[0xc9]:0x0
    reg[0xca]:0x0
    reg[0xcb]:0x0
    reg[0xcc]:0x0
    reg[0xcd]:0x0
    reg[0xce]:0x0
    reg[0xcf]:0x0
    reg[0xd0]:0x0
    reg[0xd1]:0x43
    reg[0xd2]:0x94
    reg[0xd3]:0xf
    reg[0xd4]:0x60
    reg[0xd5]:0xf2
    reg[0xd6]:0x0
    reg[0xd7]:0x3
    reg[0xd8]:0x0
    reg[0xd9]:0x0
    reg[0xda]:0x0
    reg[0xdb]:0x0
    reg[0xdc]:0x0
    reg[0xdd]:0x0
    reg[0xde]:0x0
    reg[0xdf]:0x0
    reg[0xe0]:0x0
    reg[0xe1]:0x0
    reg[0xe2]:0x0
    reg[0xe3]:0x0
    reg[0xe4]:0x0
    reg[0xe5]:0x0
    reg[0xe6]:0x0
    reg[0xe7]:0x0
    reg[0xe8]:0x0
    reg[0xe9]:0x0
    reg[0xea]:0x0
    reg[0xeb]:0x0
    reg[0xec]:0x0
    reg[0xed]:0x0
    reg[0xee]:0x0
    reg[0xef]:0x0
    reg[0xf0]:0x5f
    reg[0xf1]:0x55
    reg[0xf2]:0x42
    reg[0xf3]:0x39
    reg[0xf4]:0x36
    reg[0xf5]:0x30
    reg[0xf6]:0x0
    reg[0xf7]:0x0
    reg[0xf8]:0x0
    reg[0xf9]:0x0
    reg[0xfa]:0x0
    reg[0xfb]:0x0
    reg[0xfc]:0x0
    reg[0xfd]:0x0
    reg[0xfe]:0x0
    reg[0xff]:0x0

  • Hello Robin,

    please make sure you enable the CSI output TX in reg 0x33[0] = 1

    Also, once you have cameras connected, make sure you enable RX port forwarding in reg 0x20.

  • Hi Hamzeh,

    We  still cannot show Pattern mode, use the script as belows:

    ds90ub962_write_reg(0x33,0x01);// # CSI enable

    ds90ub962_write_reg(0xB0,0x00);// # Indirect Pattern Gen Registers
    ds90ub962_write_reg(0xB1,0x01);// # PGEN_CTL
    ds90ub962_write_reg(0xB2,0x01);//
    ds90ub962_write_reg(0xB1,0x02);// # PGEN_CFG
    ds90ub962_write_reg(0xB2,0x33);//
    ds90ub962_write_reg(0xB1,0x03);// # PGEN_CSI_DI
    ds90ub962_write_reg(0xB2,0x24);//
    ds90ub962_write_reg(0xB1,0x04);// # PGEN_LINE_SIZE1
    ds90ub962_write_reg(0xB2,0x0F);//
    ds90ub962_write_reg(0xB1,0x05);// # PGEN_LINE_SIZE0
    ds90ub962_write_reg(0xB2,0x00);//
    ds90ub962_write_reg(0xB1,0x06);// # PGEN_BAR_SIZE1
    ds90ub962_write_reg(0xB2,0x01);//
    ds90ub962_write_reg(0xB1,0x07);// # PGEN_BAR_SIZE0
    ds90ub962_write_reg(0xB2,0xE0);//
    ds90ub962_write_reg(0xB1,0x08);// # PGEN_ACT_LPF1
    ds90ub962_write_reg(0xB2,0x02);//
    ds90ub962_write_reg(0xB1,0x09);// # PGEN_ACT_LPF0
    ds90ub962_write_reg(0xB2,0xD0);//
    ds90ub962_write_reg(0xB1,0x0A);// # PGEN_TOT_LPF1
    ds90ub962_write_reg(0xB2,0x04);//
    ds90ub962_write_reg(0xB1,0x0B);// # PGEN_TOT_LPF0
    ds90ub962_write_reg(0xB2,0x1A);//
    ds90ub962_write_reg(0xB1,0x0C);// # PGEN_LINE_PD1
    ds90ub962_write_reg(0xB2,0x0C);//
    ds90ub962_write_reg(0xB1,0x0D);// # PGEN_LINE_PD0
    ds90ub962_write_reg(0xB2,0x67);//
    ds90ub962_write_reg(0xB1,0x0E);// # PGEN_VBP
    ds90ub962_write_reg(0xB2,0x21);//
    ds90ub962_write_reg(0xB1,0x0F);// # PGEN_VFP
    ds90ub962_write_reg(0xB2,0x0A);//

    ds90ub962_write_reg(0x4C, 0x01); //page to port RX0
    ds90ub962_write_reg(0x70, 0x1F); //RAW10_datatype_yuv422b10_VC0
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x12); //page to port RX1
    ds90ub962_write_reg(0x70, 0x5F); //RAW10_datatype_yuv422b10_VC1
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x24); //page to port RX2
    ds90ub962_write_reg(0x70, 0x9F); //RAW10_datatype_yuv422b10_VC2
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x38); //page to port RX3
    ds90ub962_write_reg(0x70, 0xDF); //RAW10_datatype_yuv422b10_VC3
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x20, 0x30);

    ds90ub962_write_reg(0x21, 0x14); //enable basic Synchronized forwarding for CSI port 0&1

    and dump the registers as belows:

    reg[0x0]:0x60
    reg[0x1]:0x0
    reg[0x2]:0x1e
    reg[0x3]:0x40
    reg[0x4]:0xd0
    reg[0x5]:0x1
    reg[0x6]:0x0
    reg[0x7]:0xfe
    reg[0x8]:0x1c
    reg[0x9]:0x10
    reg[0xa]:0x7a
    reg[0xb]:0x7a
    reg[0xc]:0xf
    reg[0xd]:0xb9
    reg[0xe]:0x1
    reg[0xf]:0xff
    reg[0x10]:0x0
    reg[0x11]:0x0
    reg[0x12]:0x0
    reg[0x13]:0x0
    reg[0x14]:0x0
    reg[0x15]:0x0
    reg[0x16]:0x0
    reg[0x17]:0x0
    reg[0x18]:0x1
    reg[0x19]:0x1
    reg[0x1a]:0x15
    reg[0x1b]:0x9
    reg[0x1c]:0xc3
    reg[0x1d]:0x0
    reg[0x1e]:0x4
    reg[0x1f]:0x2
    reg[0x20]:0x30
    reg[0x21]:0x14
    reg[0x22]:0x0
    reg[0x23]:0x0
    reg[0x24]:0x0
    reg[0x25]:0x0
    reg[0x26]:0x0
    reg[0x27]:0x0
    reg[0x28]:0x0
    reg[0x29]:0x0
    reg[0x2a]:0x0
    reg[0x2b]:0x0
    reg[0x2c]:0x0
    reg[0x2d]:0x0
    reg[0x2e]:0x0
    reg[0x2f]:0x0
    reg[0x30]:0x0
    reg[0x31]:0x0
    reg[0x32]:0x1
    reg[0x33]:0x1
    reg[0x34]:0x0
    reg[0x35]:0x0
    reg[0x36]:0x0
    reg[0x37]:0x3
    reg[0x38]:0x0
    reg[0x39]:0x0
    reg[0x3a]:0x0
    reg[0x3b]:0x0
    reg[0x3c]:0x0
    reg[0x3d]:0x0
    reg[0x3e]:0x0
    reg[0x3f]:0x0
    reg[0x40]:0x0
    reg[0x41]:0xa9
    reg[0x42]:0x71
    reg[0x43]:0x1
    reg[0x44]:0x0
    reg[0x45]:0x0
    reg[0x46]:0x20
    reg[0x47]:0x0
    reg[0x48]:0x0
    reg[0x49]:0x0
    reg[0x4a]:0x0
    reg[0x4b]:0x12
    reg[0x4c]:0x38
    reg[0x4d]:0xc0
    reg[0x4e]:0x2
    reg[0x4f]:0x0
    reg[0x50]:0x0
    reg[0x51]:0x0
    reg[0x52]:0x0
    reg[0x53]:0x0
    reg[0x54]:0x0
    reg[0x55]:0x0
    reg[0x56]:0x0
    reg[0x57]:0x0
    reg[0x58]:0x58
    reg[0x59]:0x0
    reg[0x5a]:0x0
    reg[0x5b]:0x0
    reg[0x5c]:0x0
    reg[0x5d]:0x0
    reg[0x5e]:0x0
    reg[0x5f]:0x0
    reg[0x60]:0x0
    reg[0x61]:0x0
    reg[0x62]:0x0
    reg[0x63]:0x0
    reg[0x64]:0x0
    reg[0x65]:0x0
    reg[0x66]:0x0
    reg[0x67]:0x0
    reg[0x68]:0x0
    reg[0x69]:0x0
    reg[0x6a]:0x0
    reg[0x6b]:0x0
    reg[0x6c]:0x0
    reg[0x6d]:0x7f
    reg[0x6e]:0xaa
    reg[0x6f]:0x88
    reg[0x70]:0xdf
    reg[0x71]:0xec
    reg[0x72]:0xe4
    reg[0x73]:0x0
    reg[0x74]:0x0
    reg[0x75]:0x0
    reg[0x76]:0x0
    reg[0x77]:0xc5
    reg[0x78]:0x0
    reg[0x79]:0x1
    reg[0x7a]:0x0
    reg[0x7b]:0x0
    reg[0x7c]:0xc0
    reg[0x7d]:0x0
    reg[0x7e]:0x0
    reg[0x7f]:0x0
    reg[0x80]:0x0
    reg[0x81]:0x0
    reg[0x82]:0x0
    reg[0x83]:0x0
    reg[0x84]:0x0
    reg[0x85]:0x0
    reg[0x86]:0x0
    reg[0x87]:0x0
    reg[0x88]:0x0
    reg[0x89]:0x0
    reg[0x8a]:0x0
    reg[0x8b]:0x0
    reg[0x8c]:0x0
    reg[0x8d]:0x0
    reg[0x8e]:0x0
    reg[0x8f]:0x0
    reg[0x90]:0x0
    reg[0x91]:0x0
    reg[0x92]:0x0
    reg[0x93]:0x0
    reg[0x94]:0x0
    reg[0x95]:0x0
    reg[0x96]:0x0
    reg[0x97]:0x0
    reg[0x98]:0x0
    reg[0x99]:0x0
    reg[0x9a]:0x0
    reg[0x9b]:0x0
    reg[0x9c]:0x0
    reg[0x9d]:0x0
    reg[0x9e]:0x0
    reg[0x9f]:0x0
    reg[0xa0]:0x0
    reg[0xa1]:0x0
    reg[0xa2]:0x0
    reg[0xa3]:0x0
    reg[0xa4]:0x0
    reg[0xa5]:0x1c
    reg[0xa6]:0x0
    reg[0xa7]:0x0
    reg[0xa8]:0x0
    reg[0xa9]:0x0
    reg[0xaa]:0x0
    reg[0xab]:0x0
    reg[0xac]:0x0
    reg[0xad]:0x0
    reg[0xae]:0x0
    reg[0xaf]:0x0
    reg[0xb0]:0x0
    reg[0xb1]:0xf
    reg[0xb2]:0xa
    reg[0xb3]:0x8
    reg[0xb4]:0x25
    reg[0xb5]:0x0
    reg[0xb6]:0x18
    reg[0xb7]:0x0
    reg[0xb8]:0x8f
    reg[0xb9]:0x33
    reg[0xba]:0x83
    reg[0xbb]:0x74
    reg[0xbc]:0x80
    reg[0xbd]:0x0
    reg[0xbe]:0x0
    reg[0xbf]:0x0
    reg[0xc0]:0x0
    reg[0xc1]:0x0
    reg[0xc2]:0x0
    reg[0xc3]:0x0
    reg[0xc4]:0x0
    reg[0xc5]:0x0
    reg[0xc6]:0x0
    reg[0xc7]:0x0
    reg[0xc8]:0x0
    reg[0xc9]:0x0
    reg[0xca]:0x0
    reg[0xcb]:0x0
    reg[0xcc]:0x0
    reg[0xcd]:0x0
    reg[0xce]:0x0
    reg[0xcf]:0x0
    reg[0xd0]:0x0
    reg[0xd1]:0x43
    reg[0xd2]:0x94
    reg[0xd3]:0x3f
    reg[0xd4]:0x60
    reg[0xd5]:0xf2
    reg[0xd6]:0x0
    reg[0xd7]:0x3
    reg[0xd8]:0x0
    reg[0xd9]:0x0
    reg[0xda]:0x0
    reg[0xdb]:0x0
    reg[0xdc]:0x0
    reg[0xdd]:0x0
    reg[0xde]:0x0
    reg[0xdf]:0x0
    reg[0xe0]:0x0
    reg[0xe1]:0x0
    reg[0xe2]:0x0
    reg[0xe3]:0x0
    reg[0xe4]:0x0
    reg[0xe5]:0x0
    reg[0xe6]:0x0
    reg[0xe7]:0x0
    reg[0xe8]:0x0
    reg[0xe9]:0x0
    reg[0xea]:0x0
    reg[0xeb]:0x0
    reg[0xec]:0x0
    reg[0xed]:0x0
    reg[0xee]:0x0
    reg[0xef]:0x0
    reg[0xf0]:0x5f
    reg[0xf1]:0x55
    reg[0xf2]:0x42
    reg[0xf3]:0x39
    reg[0xf4]:0x36
    reg[0xf5]:0x30
    reg[0xf6]:0x0
    reg[0xf7]:0x0
    reg[0xf8]:0x0
    reg[0xf9]:0x0
    reg[0xfa]:0x0
    reg[0xfb]:0x0
    reg[0xfc]:0x0
    reg[0xfd]:0x0
    reg[0xfe]:0x0
    reg[0xff]:0x0

    please help us to check, and the data type is YUV422 8BIT ?

  • Hello Robin,

    wondering why you are not using the script I sent you! It looks like you are using a totally different script.

    Please use the script I sent you; I have tested it, and it is working. If it does not work at your end, you need to check the setting of your SoC.

    Also, the following lines are not needed for Patgen. These are only needed for forwarding the incoming video data from a SER/Camera.

    ds90ub962_write_reg(0x4C, 0x01); //page to port RX0
    ds90ub962_write_reg(0x70, 0x1F); //RAW10_datatype_yuv422b10_VC0
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x12); //page to port RX1
    ds90ub962_write_reg(0x70, 0x5F); //RAW10_datatype_yuv422b10_VC1
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x24); //page to port RX2
    ds90ub962_write_reg(0x70, 0x9F); //RAW10_datatype_yuv422b10_VC2
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x4C, 0x38); //page to port RX3
    ds90ub962_write_reg(0x70, 0xDF); //RAW10_datatype_yuv422b10_VC3
    ds90ub962_write_reg(0x7C, 0xC0); //RAW10 use lower 8bit

    ds90ub962_write_reg(0x20, 0x30);

    ds90ub962_write_reg(0x21, 0x14); //enable basic Synchronized forwarding for CSI port 0&1

  • Hi Hamzeh,

    Just like I said before, the register 0x33 is 0 when using the script you sent, we did not know why, so try it myself.

    Do you have any idea that why 0x33 is 0?

    Thanks!

  • Hello Robin,

    try moving reg 0x33 writing to the end of the script and see if that works?