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SN65HVD1050A-Q1: Cannot induce dominant bus state

Part Number: SN65HVD1050A-Q1

Tool/software:

I'm working on a board where the CAN transceiver is being tested in isolation (benchtop 5V power applied for supply, no microcontroller connected to TX/RX so lines are being manually tied high/low to 5V/GND, nothing connected to bus pins, no cables or other devices). The TX input is pulled high to 5V, so when I measure the bus lines I see the expected recessive state voltages of ~2.2V.

However, when I manually connect TX (TP5 in this example) to ground for the transceiver to assert a dominant bus state there is no change in the bus voltages. It seems that the transceiver is not asserting a dominant state on the bus. I've verified at the pins of the transceiver that TX is 0V, that 5V power is being delivered, and that pin 8 is tied to 0V. The transceiver is clearly still functioning because the bus is in a recessive state.

The intended test was the verify the voltage levels with the transceiver asserting a dominant state, but it does not seem to be able to do so. Is there something missing from the setup, or else what could the cause of the issue be?

  • Hi Matthew,

    Thanks for sharing your question on E2E. 

    This device has a dominant timeout feature that prevents the driver from holding the bus dominant for too long. When testing manually, tying TXD low will cause the device to drive the bus dominant for only the dominant timeout time (700us max) before the driver returns to a recessive state. In order to evaluate the dominant-state specifications, I recommend setting your oscilloscope to trigger on the dominant-to-recessive transition only once so that the 700us dominant period can be observed. 

    Let me know if this seems to be what your were running into and if you have any more questions. 

    Regards, 
    Eric Schott