Tool/software:
Hi Team,
I would like to check if there is a scenario that our crystal can't output REFCLK to 936 well. Do we see the black screen or the 935/936 would switch to internal CLK to generate the PCLK?
Regards,
Roy
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Tool/software:
Hi Team,
I would like to check if there is a scenario that our crystal can't output REFCLK to 936 well. Do we see the black screen or the 935/936 would switch to internal CLK to generate the PCLK?
Regards,
Roy
Hi Roy,
The deserializer requires a refclk in all cases. The UB936 has an internal reference clock, however it is not as accurate as the external oscillators which are used. This is intended for startup only.
Best,
Thomas
Hi Thomas,
Yes, I agree your comments, but we met a weird condition. In normal case, the crystal can output the correct REFCLK waveform.
But when issue(REFCLK didn't output the correct waveform, but '0' level) occurred, the 935/936 can normally output the correct timing.
Regards,
Roy
Hi Zoe,
If we removed the REFCLK before powering up the 935/936, but we didn't set above bit. The 936 can't work. Why the 936 don't use internal AON clock at this time?
In addition, may you let me know the full name of AON?
Regards,
Roy
Hi Roy,
What do you mean by 936 can't work in this context? AON clock stands for always on clock. The AON clock is not intended to be used for lock between the 935/936 during operation. It is intended to be used so that registers can still be accessed and written while REFCLK is not detected present at start-up. A REFCLK is required for operation.
Best,
Zoe
Hi Zoe,
Thanks for information.
We have one scenario is that 935/936 are normally work in the beginning with using 936 external REFCLK. But due to some reasons, the 936 external REFCLK is stopped, but the 935/936 can still transmit the data, but the FPD-link seems to be unstable.
1. Do you think above state is reasonable? Do you think 936 use internal CLK when the REFCLK stopped?
But after we set the bit = '1'. When the REFCLK stopped. The 935/936 will instantly stopped and show the black screen.
2. I think the above result is ok to me.
But I am not sure how to explain the first result.
Regards,
Roy
Hi Roy,
For the first phenomenon, we would expect to see this behavior. If the REFCLK input is stopped, the devices will transition to the always on clock. The clock is not intended to be used for operation due to the potential instability on the FPD-Link operation that was observed. The AON clock will have a variation of 25MHz +/- 10% and each device will not have the same performance when REFCLK is lost. The internal clock can be used to access the deserializer however, it should not be intended to be used for normal operation.
When the bit '1' was set, video data was lost as the REFCLK is forced to be found present.
Best,
Zoe