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DS90UB960-Q1: Devkit compatibility and channel speed configurability

Matt Calvo
Genius 14755 points
Part Number: DS90UB960-Q1
Other Parts Discussed in Thread: DS90UB953-Q1

Tool/software:

Hey FPD-Link team,

I have a customer using the DS90UB960-Q1 and the DS90UB953-Q1 on a project and we were hoping you could help to provide some guidance on two items. See below:

  • We were having stability issues with capture on our setup that uses ub960 as deserializer and ub953 as serializers on a custom platform. We are trying to do some platform independent testing with an NVIDIA devkit instead of our custom hardware to try and pinpoint what is causing the huge number of CRC errors and constant channel unlocks that we are getting. Our idea is to ideally use the ub960 EVM, with the Xavier NX devkit, but said evm uses Mipi-60 as the csi-2 outputs. And the devkit uses ribbons as the csi-2 inputs, see image below. We wanted to check if there is any other evaluation kit or adapter that can meet our needs to have ribbons as the NVIDIA Xavier NX devkit uses. Is there an adapter or another evaluation kit that uses the UB960, that is compatible with NVIDIA's Jetson Xavier NX devkit? 

  • Regarding the forward channel's speed, we are using Synchronous mode and from our understanding, this mode uses a REFCLK that goes to the deserializer to provide via the back channel a clk for the serializer. We wanted to try and reduce/change the speed of it to see if the stability improves/changes. However, on our current platform and from looking at the datasheets we seem to be stuck with the speed that the refclk dictates, in our case 4Gbps with a 25MHz refclk. Is there a SW based way of using register configuration to change the forward channel's speed without altering the hw, i.e. keeping the current mode resistors or crystal osc?

Best regards,

Matt

  • 0
    TI__Mastermind 23725 points

    Hi Matt, 

    Unfortunately, we do not have different evaluation kits for the UB960. To use the CSI-2 connector here, an adapter card would be needed for a QTH to FFC connector on the DevKit. 

    Regarding the forward channel rate change, this would require a hardware change. As mentioned in your post, the back channel rate will change when the REFCLK input to the UB960 is changed. One potential option only using software is to change modes from synchronous to non-synchronous mode. This is done by setting the back channel rate to 10Mbps in register 0x58 of the UB960. The 953 can then use the internal AON clock to generate the forward channel. One thing to note is that this would only be testing a different mode of the serializer/deserializer, not changing the forward channel rate. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Hi, Zoe

    Thanks for the reply,

    Ok will look into an adapter for the EVM.

    And let me see if I got the mode reply correctly, so we change 0x58 and the serializer will now use its internal clk as refclk for the forward channel, but since the deserializer already has its refclk, the forward channel rate won't change.

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres, 

    Andres Artavia said:
    And let me see if I got the mode reply correctly, so we change 0x58 and the serializer will now use its internal clk as refclk for the forward channel, but since the deserializer already has its refclk, the forward channel rate won't change.

    Here is the procedure to switch to internal AON mode on the 953: 

    1. Select deserializer RX port in register 0x4C
    2. Configure deserializer for 10Mbps BC rate in register 0x58
    3. On the serializer configure the AON mode by writing 0x03=0x5B

    This will separate the forward channel from the reference clock on the deserializer but maintain the same forward channel rate. This is the one change that can be made for debugging without hardware changes

    In order to change the forward channel rate, the refclk would need to be changed. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Got it. Thank you so much for the clarification and the quick response.

    Regards,

    Andres

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Maybe to add a bit of context into what we are experiencing and what we are trying to achieve.

    We observed lots of link unlock & CRC errors in our logs for UB960.
    Based on the FPD link eye diagram measurements, the signal quality (the width of the LVDS eye at 4Gbps) has decreased from 148.7 ps to 94.6 ps, indicating a 36% deterioration. This significant drop is a primary reason for our consideration of reducing the link speed to investigate potential workarounds for compensating the signal loss.
    Our questions are as follows:

    1.Would reducing the link speed to 2Gbps help mitigate the unlock and CRC issues?
    2.Given the 36% deterioration observed in the eye diagram, does this suggest that a PCB redesign might be the only option to enhance LVDS signal quality?

    Thank you for your assistance!

    Regards,

    Andres

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres, 

    There are various factors that can impact the eye diagram measurements from a system level perspective. Would you be able to provide some more information on a system level here? Is the eye diagram measurement including the cable? If so, what cable is being used and what is its length? 

    Best,

    Zoe

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres,

    Some additional things to note and to answer some of your questions here: 

    Andres Artavia said:
    1.Would reducing the link speed to 2Gbps help mitigate the unlock and CRC issues?

    There is no guarantee reducing the speed to 2Gbps would solve the issue here but, could help narrow down the issue. For testing this can be done by writing 0x58[2:0] = 101 for 25Mbps. Please note this should only be used for testing. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Ok thanks, will try that. 
    In regards to your previous question:
    The measurement was taken on both ends, the serializer side was ok, but the deserializer's input had the eye issue. They tested with a short cable and long one, and saw the same results.

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres, 

    Let me know if there are any improvements using the lower back channel rate. 

    Additionally, have S-parameter measurements been taken for the total system? 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Hi,

    We we able to apply the register changes and get video out, albeit at a lower resolution. We will start testing with it. 

    To reply to the S parameter question, the S parameter measurements were taken by the designer a while back, but we dont have them at hand.

    We also were wondering about why is this a temporary solution? Just asking in case we see a better behavior.

    Regards,

    Andres

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres, 

    We would consider this a temporary solution as the 25Mbps is not a supported back channel speed on the UB960. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    Prodigy 100 points

    Hi,

    We were able to get capture with that register change, with a lower resolution but were able to get videos. However the CRC and channel unlocks situation remained the same. Is there something else we can try, register wise before embarking on hardware/layout changes?

    Regards,

    Andres

  • 0 in reply to Andres Artavia
    Prodigy 100 points

    From your experience, have you seen situations were slowing the speed down, doesn't has any effect on the link stability?

  • 0 in reply to Andres Artavia
    TI__Mastermind 23725 points

    Hi Andres, 

    Yes, slowing down the speed shouldn't impact the link stability. When designing FPD-Link systems we provide a channel specification document for customers to design their system to. The channel specification will define the allowable insertion and return loss across the entire frequency range of operation. 

    Have you measured S-parameter results in the system? The link stability issue here points to a potential issue on the hardware side. 

    Best,

    Zoe