TDES954: How to improve margin test performance on custom board?

Hello Nimesh,

Have you tested with a different cable type / length?

Have you tested with different boards?

I checked the SER and DES schematics, and everything looks good.

However, I have noticed that you are using different AC-coupling capacitors on both sides. On the SER you have 100nF and 47nF but on the DES 47nF and 22nF. These different values make the result in the series caps (100nF and 47nF) = 32nF which is not equivalent to any of the used termination caps (47nF and 22nF). This may lead to some reflections of the transmitter/receiver on the SER/DES.

Additionally, you may have not optimal layout which could impact the link quality.

Hello Hamzeh,

Thank you for your prompt reply.

Attached, you will find the margin test results for both 2-meter and 5-meter cables after we changed the AC capacitors on the deserializer side. Specifically, C320 has been updated to 0.1uF_50V_0402 and C321 to 0.047uF_50V_0402, matching the values present on the serializer. Unfortunately, we are still observing poor margin test results.

Additionally, I've included layout screenshots of the deserializer U52 as follows:

1. Combined view of Layer 1 (TOP), Layer 2, and Layer 3

2. Layer 1 (TOP) only

3. Layer 2 (GND) only

4. Layer 3 (GND) only

   • We have routed both traces (DES1_RIN0_P and DES1_RIN1_P) with 50E impedance on the TOP layer (Layer 1) while providing a void in the next layer (Layer 2) and a plane in the subsequent layer (Layer 3).

Could you please provide your suggestions to improve the margin test results?

Hello Nimesh,

there are few changes on the layout which could improve the performance. But before going into that direction, I want you to test/answer the following:

1) Which data rate are you using? i.e. what is the image sensor resolution, data type and frame rate?

2) Can you test your margin again after disconnecting the PoC on both sides? You just need to desolder the first inductor (2.2uF) and supply the camera locally with a lab power-supply.

Hamzeh Jaradat said:

1) We operate V3Link in synchronous mode, at 4.0 Gbps (25 MHz ref clock), The image sensor operates in RAW10 format, at 120 fps @ 728x544 or at 60 fps @ 1456x1088. The CSI bandwidth is 1.2 Gbps.

2) We tested here with 1m cable. 2m and 5m cable and observing same behavior with different boards as well. 

3) For last suggestion of isolating inductor, we are facing some setup issue that blocking us to share results, we will try to solve and share you result soon. 

Regards,

Nimesh Rana

Ok, thanks. Waiting for your feedback.

Question, why do you think the above MAP results are bad? I can see you have a good margin with AEQ settings from 0 to 5.

Hello Hamzeh, 

Ragarding your query, "why do you think the above MAP results are bad? I can see you have a good margin with AEQ settings from 0 to 5"even though good margin with current hardware we are observing stability issue for video streaming, which is not with Proto hardware that we are taking for benchmarking. 

Also we tried your suggestion by applying local power supply to camera module by isolating inductor (2.2uf), we can see some improvement but not matching with one which we benchmarked for comparision. You can refer below image for your reference. 

Test Result Data: By applying local power supply to camera module 

Refer below image which we are benchmarking for test resut comparision, that has been derived from different hardware (Proto board) wher same de serializer IC present, camera module is same we used with current setup. 

Proto_Board schematics.pdf

I have also atatched design implementation of proto board for your reference, difference is POC network used in proto board supports 250mA current out rating, where as current hardware where we are facing issue having POC network to support 500mA rating. 

Please guide us if any hardware or software change can help to get result near to benchmark image.  

Regards,

Nimesh Rana

Hello Nimesh,

on your Schematic there is nothing which can be improved.

If you want a detailed Layout review, please send ODB++ or Gerber files.

Hello Hamzeh, 

Thanks for the confirmation on schematic. For layout file, we can not share here in open forum. Request you to share personal email address where we can share requrie file 1:1. 

Regards,

Nimesh Rana

Hi Nimesh,

you can send to: h-jaradat(at)ti(dot)com