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DP83640: Regarding the internal IEEE 1588 clock/timer vs absolute network ptp time

mc b
Prodigy 175 points
Part Number: DP83640


Tool/software:

Greetings,

I'd like to clarify some details I've gathered:

Q1-) Regarding the DP83640's internal IEEE 1588 clock/timer, my understanding is that it starts either from zero or another predefined value, but it's not automatically updated by the PTP master. To put it differently, we must still adhere to the PTP protocol through host software (such as MCU or CPU), correct? However, the relative timestamps T1, T2, T3, and T4 are taken from the DP83640 itself, correct? My point is that the internal IEEE 1588 timer of the DP83640 doesn’t provide direct UTC time; instead, it only offers relative timing in a 64-bit format—32 bits for seconds, 30 bits for nanoseconds, and 2 bits for fractional nanoseconds—without being able to synchronize with a PTP master on its own, is that correct?

Q-2) I'm curious about how the IEEE 1588 timer's timestamps correspond with the DP83640's internal 250 MHz clock, as mentioned in the AN-1730 DP83640 Synchronous Ethernet Mode document. What I'm trying to get at is, if the IEEE 1588 timer's smallest unit of time is fractional nanoseconds, shown in the first two bits, and the DP83640 clock operates at 250 MHz (equating to 4 ns increments), how does it handle these smaller units? Are the fractional bits always set to zero?

"PTP Clock: A PTP clock is the source of an output clock signal which is locked to a PTP counter. In the DP83640, the local PTP clock operates at 250 MHz, and can be configured to control the CLK_OUT signal. This PTP CLK_OUT signal is programmable to frequencies which are integral divisions of the 250 MHz PTP clock in the range of 2 and 255 (125 MHz to 0.98 MHz).

PTP Counter: A PTP counter contains time information, and is locked to the PTP clock. In a master node, the PTP counter is the source of data used in the Precision Time Protocol for the purpose of synchronizing counters in PTP slave nodes. The PTP counter is incremented every 8 ns. Local Reference Clock: A local reference clock is used for generating network traffic. The local reference clock is embedded into the transmit network packet traffic and is recovered from the network packet traffic at the receiver node. All Ethernet Physical Layer devices use

  • 0
    TI__Mastermind 40625 points

    Hello,

    I would like to preface this reply with the statement that DP83640 is an older device and thus support is strictly limited to the datasheet and other existing documents from TI. 

    1) The PHY should be able to act as a pseudo-master once PTP exchange is done. Perhaps CLKOUT can be used to provide this system-wise.

    2) According to datasheet, PHY has ability to record within 2x10^-32 ns.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 175 points

    Greetings Gerome,

    Thank you for your response, however, I'm still unclear on certain aspects regarding the DP83640's IEEE 1588 functionality and its internal timer/clock. I would highly appreciate it if you could provide more detailed answers to my specific questions:

    1. When using the DP83640 in a precision time protocol (PTP) environment, does its internal IEEE 1588 clock/timer automatically synchronize with the PTP master, or is manual intervention required via the host application software? Furthermore, could you confirm that the DP83640 is responsible for generating the timestamps T1, T2, T3, and T4? Does the PHY's internal IEEE 1588 timer reflect a simple count from an arbitrary start time or is there a feature that allows it to sync directly to a real-time clock (RTC), providing time-of-day information?

    2. Could you clarify how the IEEE 1588 timer's fractional nanosecond capabilities are supported by the DP83640's internal 250 MHz clock that notably runs in 4 ns increments? Specifically, are the fractional nanosecond bits handled in hardware, and if so, how?

    I'm trying to better understand how the timekeeping functions relate to the capabilities described in the AN-1730 DP83640 Synchronous Ethernet Mode document, and these technical points are very important for my application. Thank you in advance for indulging my request for this detailed explanation.

    Best regards,

  • 0 in reply to mc b
    TI__Mastermind 40625 points

    Hello,

    Inherently, the PHY will not synchronize with the PTP master. This has to be done in application. The PHY has tools to be able to timestamp in efforts to assist the SoC, but ultimately the processing has to be done in the MAC side.

    I cannot diverge more information on the fractional nanosecond capabilities other than the 250MHz clock is not solely responsible for how much resolution the PHY has, but the PHY does support fractional nanosecond capabilities. 

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 175 points

    I confused , https://www.ti.com/lit/ds/symlink/dp83640.pdf?ts=1726188396638 

    6.1.1.1 IEEE 1588 Synchronized Clock tells us like this 

    "The clock consists of the following fields: Seconds (32–bit field), Nanoseconds (30–bit field), and Fractional Nanoseconds (units of 2 -32 ns)."

    so you say "but the PHY does support fractional nanosecond capabilities" , so i am asking do we need to expect the last 2 bits as 0 since they are Fractional Nanoseconds ? 

  • 0 in reply to mc b
    TI__Mastermind 40625 points

    Hello,

    This statement says that the clocking can be adjusted in the appropriate fields. The PHY's timestamping is such where the MAC should be able to determine what adjustments are needed and the ability to configure the clock within 2EE-32 ns.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 175 points

    Thank you for the continued support, Gerome. I have come across information that appears to present a conflict of definitions and I would appreciate your assistance in resolving my confusion.

    1. In the device overview of the DP83640 datasheet, under the "Features" section, it's stated that the timestamp resolution is 8 nanoseconds. This seems to imply that the timing granularity the device operates with is in 8 ns increments. Here's the datasheet link for your reference: DP83640 Datasheet

    2. Similarly, the application note SNLA100A, under "Key Terms", mentions that "The PTP counter... is incremented every 8 ns." The application note can be found here: SNLA100A Application Note

    3. You mentioned earlier that the PHY does indeed support fractional nanosecond capabilities, which suggests a far greater time precision than 8 ns.

    Could you please clarify how the DP83640 supports timestamping at the fractional nanosecond level when the datasheet and associated application note specify an 8 ns resolution? It would be particularly helpful if you could explain the role of the fractional nanosecond timestamping feature and how it aligns with the 8 ns counter increment. Does this mean that the PHY is capable of capturing time more precisely than what is suggested by the 8 ns increments mentioned in the documents?

    Thank you for your time and I look forward to your clarification.

  • 0 in reply to mc b
    TI__Mastermind 40625 points

    Hello,

    Think of the 8ns as how often the PHY can execute any adjustment that needs to be done to synchronize the clocks. Every 8ns, PHY has the opportunity to tweak the clock in the seconds, nano-seconds, or even fractional nano-seconds which is what is described in the datasheet. The application is responsible for determining the actual adjustment required, and the timestamping done by the PHY and link partner should provide enough information to execute the appropriate calculation and subsequent adjustment required on PHY.

    Sincerely,

    Gerome