Tool/software:
Hello,
On a custom board, we are using the DP83867IR device with the SMI operating at 25 MHz and 3.3V. The MDIO line is pulled-up to 3.3V using a 1.5K resistor as specified in IEEE 802..3 clause 22 standard.
We use one FPGA acting as the "station" and 3 DP83867 PHYs. We operate transactions without any preamble as this is supposed to be supported by the PHY.
We have trouble with this interface: successive transactions fail to be effectively taken into account by the Phy under certain conditions (same behaviour for all three PHYs).
MDC and MDIO signals are clean (no signal intergrity issue) and timings constraints (setup/hold times) are met with several ns of margin.
Everything seems fine when transactions (in any order or combination of reads and writes) are spaced out by about 1.3 µs (which looks like being 32 clock cycles at 25MHz).
When successive transactions occur with less than 1.3 µs between the end of the first one and the beginning of the second one, the transaction sometimes fails:
- for reads, the PHY does not drive the MDIO line, resulting in reading 0xFFFF
- for writes, they have no effect (reading the value afterward shows that the target register value was not changed)
We have noticed that the issue only shows up when the last bit of the first transaction frame is a '0'.
When the last bit of a frame is '0', it takes several tens of ns before the MDIO line reaches the logic '1' level (Vih_min = 1.7V) once the transaction is ended. We measured around 100 ns in our application which is consistent which what could be expected (time constant RC = 1.5K * 66 pF). Then, the MDIO line may be sampled at a low level by the Phy on the next rising edge following the end of a transaction.
Whereas when the last bit of the frame is '1', the MDIO line is already high when the transaction effectively ends.The Phy then always samples a high level on the next rising edge following the end of a transaction.
This is the only difference, we guess, may explain the observed behaviour: we wonder if the Phy may detect a "false" start of transaction (that is a '01' pattern) which is then considered invalid as the following opcode is neither 10 or 01. In such situation, as stated in the BMSR bit 6 description, the Phy would require that the sation issues a Preamble (MDIO being high for 32 clock cycles) before being able to respond to new transactions.
Do you confirm our anlysis? Are there constraints we are not aware of when operating the SMI as we do?
Thanks for yout help.
Regards,
Nicolas
