DS90UB941AS-Q1: Link not detected

Hi, to get LOCK and link detect, the SER-DES pair have to be set to compatible modes with the MODE_SEL (device functional modes) settings and video enabled (either with DSI input to 941AS from the SoC or Pattern Generation enabled. 

The mode selections are device specific eg. with the 941AS there are mode settings DSI number of lanes, clock source, DSI enable, and STP or Coax cabling used. Can you please check these:

- 941AS register 0x13 "TX_MODE_STS"
- 948 register bits 0x23 [4:2] (MODE_SEL1) and 0x49 (MODE_SEL0)

Best regards,
Ikram

- 941 AS register 0x13 "TX_MODE_STS"    The value of this is 0x8c based on the bootstrap.

I tried to set dsi lanes(4) and splitter mode(0). (By setting 0x4F register with value 0x8C)

But still link detect remains 0.

Register Dump:

root@ospux-v920:~# i2cdump -f -y 10 0xc
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 18 00 00 92 00 00 00 00 00 01 00 00 04 30 00 00 ?..?.....?..?0..
10: 00 00 00 8c 00 00 fe 1e 7f 7f 01 00 00 00 01 00 ...?..?????...?.
20: 00 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a ..%.....? ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02 .?.??.........??
40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 ac ??.............?
50: 16 00 00 00 02 10 00 02 00 00 09 07 07 06 44 21 ?...??.?..????D!
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 "?..?......... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 81 00 ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 82 00 40 00 00 00 40 00 00 00 00 02 ff 00 ..?.@...@....?..
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 82 00 40 08 00 00 00 00 00 00 00 02 00 00 ..?.@?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 _UB941..........

Hi, do you have a local I2C connection to the 948 deserializer? If so, could you get a register dump, and also check the mode selections?

One the 941AS board, are you able to connect I2C via USB2ANY or Aardvark so that we can use the ALP (TI FPD-link API) software? Then, could you please enable PatGen and check whether you can get LOCK. Let me know if you have questions about this step.


Best regards,
Ikram

Register dump of the deserializer on display:
Deserializer
0x34 0xFF 0x00 r OK
0x34 0xFF 0x00 r OK
0x34 0xFF 0x00 r OK
0x34 0xFE 0x00 r OK
0x34 0xFD 0x00 r OK
0x34 0xFC 0x00 r OK
0x34 0xFB 0x00 r OK
0x34 0xFA 0x00 r OK
0x34 0xF9 0x00 r OK
0x34 0xF8 0x00 r OK
0x34 0xF7 0x00 r OK
0x34 0xF6 0x00 r OK
0x34 0xF5 0x38 r OK
0x34 0xF4 0x34 r OK
0x34 0xF3 0x39 r OK
0x34 0xF2 0x48 r OK
0x34 0xF1 0x55 r OK
0x34 0xF0 0x5F r OK
0x34 0xEF 0x00 r OK
0x34 0xEE 0x00 r OK
0x34 0xED 0x00 r OK
0x34 0xEC 0x00 r OK
0x34 0xEB 0x00 r OK
0x34 0xEA 0x00 r OK
0x34 0xE9 0x00 r OK
0x34 0xE8 0x00 r OK
0x34 0xE7 0x00 r OK
0x34 0xE6 0x00 r OK
0x34 0xE5 0x00 r OK
0x34 0xE4 0x00 r OK
0x34 0xE3 0x00 r OK
0x34 0xE2 0x00 r OK
0x34 0xE1 0x00 r OK
0x34 0xE0 0x00 r OK
0x34 0xDF 0x00 r OK
0x34 0xDE 0x00 r OK
0x34 0xDD 0x00 r OK
0x34 0xDC 0x00 r OK
0x34 0xDB 0x00 r OK
0x34 0xDA 0x00 r OK
0x34 0xD9 0x00 r OK
0x34 0xD8 0x00 r OK
0x34 0xD7 0x00 r OK
0x34 0xD6 0x00 r OK
0x34 0xD5 0x00 r OK
0x34 0xD4 0x00 r OK
0x34 0xD3 0x00 r OK
0x34 0xD2 0x00 r OK
0x34 0xD1 0x00 r OK
0x34 0xD0 0x00 r OK
0x34 0xCF 0x00 r OK
0x34 0xCE 0x00 r OK
0x34 0xCD 0x00 r OK
0x34 0xCC 0x00 r OK
0x34 0xCB 0x00 r OK
0x34 0xCA 0x00 r OK
0x34 0xC9 0x00 r OK
0x34 0xC8 0xC0 r OK
0x34 0xC7 0x00 r OK
0x34 0xC6 0x00 r OK
0x34 0xC5 0x00 r OK
0x34 0xC4 0x00 r OK
0x34 0xC3 0x00 r OK
0x34 0xC2 0x00 r OK
0x34 0xC1 0x00 r OK
0x34 0xC0 0x00 r OK
0x34 0xBF 0x00 r OK
0x34 0xBE 0x00 r OK
0x34 0xBD 0x00 r OK
0x34 0xBC 0x00 r OK
0x34 0xBB 0x00 r OK
0x34 0xBA 0x00 r OK
0x34 0xB9 0x00 r OK
0x34 0xB9 0x00 r OK
0x34 0xB8 0x00 r OK
0x34 0xB7 0x00 r OK
0x34 0xB6 0x00 r OK
0x34 0xB5 0x00 r OK
0x34 0xB4 0x00 r OK
0x34 0xB3 0x00 r OK
0x34 0xB2 0x00 r OK
0x34 0xB1 0x00 r OK
0x34 0xB0 0x00 r OK
0x34 0xAF 0x00 r OK
0x34 0xAE 0x00 r OK
0x34 0xAE 0x00 r OK
0x34 0xAD 0x00 r OK
0x34 0xAC 0x00 r OK
0x34 0xAB 0x00 r OK
0x34 0xAA 0x00 r OK
0x34 0xA9 0x00 r OK
0x34 0xA8 0x00 r OK
0x34 0xA7 0x00 r OK
0x34 0xA6 0x00 r OK
0x34 0xA5 0x00 r OK
0x34 0xA4 0x00 r OK
0x34 0xA3 0x00 r OK
0x34 0xA2 0x8C r OK
0x34 0xA1 0x00 r OK
0x34 0xA0 0x00 r OK
0x34 0x9F 0x00 r OK
0x34 0x9E 0x00 r OK
0x34 0x9D 0x00 r OK
0x34 0x9C 0x00 r OK
0x34 0x9B 0x00 r OK
0x34 0x9A 0x00 r OK
0x34 0x99 0x00 r OK
0x34 0x98 0x00 r OK
0x34 0x97 0x00 r OK
0x34 0x96 0x00 r OK
0x34 0x95 0x00 r OK
0x34 0x94 0x00 r OK
0x34 0x93 0x00 r OK
0x34 0x92 0x00 r OK
0x34 0x91 0x00 r OK
0x34 0x90 0x00 r OK
0x34 0x8F 0x00 r OK
0x34 0x8E 0x00 r OK
0x34 0x8D 0x00 r OK
0x34 0x8C 0x00 r OK
0x34 0x8B 0x00 r OK
0x34 0x8A 0x00 r OK
0x34 0x89 0x00 r OK
0x34 0x88 0x00 r OK
0x34 0x87 0x00 r OK
0x34 0x86 0x00 r OK
0x34 0x85 0x00 r OK
0x34 0x84 0x00 r OK
0x34 0x83 0x00 r OK
0x34 0x82 0x00 r OK
0x34 0x81 0x00 r OK
0x34 0x80 0x00 r OK
0x34 0x7F 0x00 r OK
0x34 0x7E 0x00 r OK
0x34 0x7D 0x00 r OK
0x34 0x7C 0x02 r OK
0x34 0x7B 0x6D r OK
0x34 0x7A 0x00 r OK
0x34 0x79 0x00 r OK
0x34 0x78 0x00 r OK
0x34 0x77 0x00 r OK
0x34 0x76 0x00 r OK
0x34 0x75 0x08 r OK
0x34 0x74 0x07 r OK
0x34 0x73 0x07 r OK
0x34 0x72 0x00 r OK
0x34 0x71 0x00 r OK
0x34 0x70 0x00 r OK
0x34 0x6F 0x00 r OK
0x34 0x6E 0x00 r OK
0x34 0x6D 0x00 r OK
0x34 0x6C 0x00 r OK
0x34 0x6B 0x00 r OK
0x34 0x6A 0x00 r OK
0x34 0x69 0x00 r OK
0x34 0x68 0x00 r OK
0x34 0x67 0x00 r OK
0x34 0x66 0x00 r OK
0x34 0x65 0x00 r OK
0x34 0x64 0x10 r OK
0x34 0x63 0x00 r OK
0x34 0x62 0x00 r OK
0x34 0x61 0x00 r OK
0x34 0x60 0x00 r OK
0x34 0x5F 0x00 r OK
0x34 0x5E 0x00 r OK
0x34 0x5D 0x00 r OK
0x34 0x5C 0x00 r OK
0x34 0x5B 0x20 r OK
0x34 0x5A 0x20 r OK
0x34 0x59 0x7F r OK
0x34 0x58 0x00 r OK
0x34 0x57 0x00 r OK
0x34 0x56 0x00 r OK
0x34 0x55 0x00 r OK
0x34 0x54 0x80 r OK
0x34 0x53 0x01 r OK
0x34 0x52 0x00 r OK
0x34 0x51 0x10 r OK
0x34 0x50 0x03 r OK
0x34 0x4F 0x00 r OK
0x34 0x4E 0x63 r OK
0x34 0x4D 0x00 r OK
0x34 0x4C 0x00 r OK
0x34 0x4B 0x08 r OK
0x34 0x4A 0x00 r OK
0x34 0x49 0x80 r OK
0x34 0x48 0x0F r OK
0x34 0x47 0x00 r OK
0x34 0x46 0x00 r OK
0x34 0x45 0x88 r OK
0x34 0x44 0x60 r OK
0x34 0x43 0x00 r OK
0x34 0x42 0x03 r OK
0x34 0x41 0x03 r OK
0x34 0x40 0x43 r OK
0x34 0x3F 0x00 r OK
0x34 0x3E 0x23 r OK
0x34 0x3D 0xC0 r OK
0x34 0x3C 0x20 r OK
0x34 0x3B 0x07 r OK
0x34 0x3A 0x00 r OK
0x34 0x39 0x00 r OK
0x34 0x38 0x00 r OK
0x34 0x37 0xAC r OK
0x34 0x36 0x00 r OK
0x34 0x35 0x00 r OK
0x34 0x34 0x01 r OK
0x34 0x33 0x25 r OK
0x34 0x32 0x90 r OK
0x34 0x31 0x00 r OK
0x34 0x30 0x00 r OK
0x34 0x2F 0x00 r OK
0x34 0x2E 0x00 r OK
0x34 0x2D 0x00 r OK
0x34 0x2C 0x00 r OK
0x34 0x2B 0x00 r OK
0x34 0x2A 0x00 r OK
0x34 0x29 0x00 r OK
0x34 0x28 0x11 r OK
0x34 0x27 0x84 r OK
0x34 0x26 0x83 r OK
0x34 0x25 0x00 r OK
0x34 0x24 0x08 r OK
0x34 0x23 0x30 r OK
0x34 0x22 0x40 r OK
0x34 0x21 0x00 r OK
0x34 0x20 0x00 r OK
0x34 0x1F 0x00 r OK
0x34 0x1E 0x00 r OK
0x34 0x1D 0x10 r OK
0x34 0x1C 0x3B r OK
0x34 0x1B 0x00 r OK
0x34 0x1A 0x00 r OK
0x34 0x19 0x01 r OK
0x34 0x18 0x00 r OK
0x34 0x17 0x00 r OK
0x34 0x16 0x00 r OK
0x34 0x15 0x00 r OK
0x34 0x14 0x00 r OK
0x34 0x13 0x00 r OK
0x34 0x12 0x00 r OK
0x34 0x11 0x00 r OK
0x34 0x10 0x00 r OK
0x34 0x0F 0x00 r OK
0x34 0x0E 0x00 r OK
0x34 0x0D 0x00 r OK
0x34 0x0C 0x00 r OK
0x34 0x0B 0x00 r OK
0x34 0x0A 0x00 r OK
0x34 0x09 0x00 r OK
0x34 0x08 0x00 r OK
0x34 0x07 0x18 r OK
0x34 0x06 0x00 r OK
0x34 0x05 0x1E r OK
0x34 0x04 0xFE r OK
0x34 0x03 0xF0 r OK
0x34 0x02 0x00 r OK
0x34 0x01 0x04 r OK
0x34 0x00 0x68 r OK

Mode selections based on the register:

010: 20 Mbps/STP (#3 on MODE_SEL1)

100: Dual OLDI output (#5 on MODE_SEL0)

Hi, could you please try these two steps:

1. On 941AS SER,
          - set register 0x56  = 0x2
          - soft reset. register 0x1 = 0x1
          - Check if link is detected to DES. Read SER 0xC register
          - read register 0x0 (or any other register) from the DES. The DES ID is 0x68 (8-bit)

2. If you can access the SER with the ALP software, please turn on Pattern Generator and see if you can get LOCK with deserializer.


- Ikram
          

Hi,

I tried to set 0x56 as you mentioned. But still link detect fails.

Meanwhile, here is our hardware setup:

Dsi from soc is connected to dsi0 on serializer. dsi1 is left unconnected.

Bootstrap configuration at serializer:

1. Single dsi input

2. 1 display connected at output.

3. Splitter mode is disabled.

Reg dump by default:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 18 00 00 92 00 00 00 00 00 01 00 00 04 30 00 00 ?..?.....?..?0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00 ...?..?????...?.
20: 00 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a ..%.....? ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02 .?.??.........??
40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c ??.............?
50: 16 00 00 00 02 00 00 02 00 00 09 00 07 06 44 8f ?...?..?..?.??D?
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 "?..?......... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 81 00 ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 82 00 40 00 00 00 40 00 00 00 00 02 ff 00 ..?.@...@....?..
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 82 00 40 08 00 00 00 00 00 00 00 02 00 00 ..?.@?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 _UB941..........

Link detect after following settings:

root@ospux-v920:~# i2cset -y 10 0xc 0x56 0x02 b
root@ospux-v920:~# i2cset -y 10 0xc 0x1 0x01 b
root@ospux-v920:~#
root@ospux-v920:~# i2cget -y 10 0x0c 0xc b
0x04

root@ospux-v920:~# i2cdetect -y -r 10
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- 0c -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UU
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --

Please clarify if any other registers to be configured.

Hi, 

I think the issue might be that the DSI rate. On the EDID image you shared, it's 157 MHz PCLK. To support that speed, the FPD-link ha to be in dual-link mode.

Datasheet states that: 
– Single link: up to 105MHz pixel clock
– Dual link: up to 210MHz pixel clock"

Register 0x5B on the SER is 0x7, indicating "111 : Forced Splitter Mode (half of video stream on each port)"

1. Can you please check that both the 941AS ports are connected via cable to the 948? DOUT0 and DOUT1

2. If you have ALP installed, you can use it to set a test pattern output. This would generate a pattern internally from the 941AS and output to the 948. You can also change the PCLK rates, so that for testing purposes you can verify that a PCLK less than 105 MHz is working with single-link mode. Let me know if you have any questions about using ALP for the pattern generation.

Best regards,
Ikram

Hi Ikram,

        Myself Rajesh and I am working along with Gayathri to bring up this Display. After your last suggestion, we tried below steps and still could not see a link lock. Kindly suggest.

 1. Can you please check that both the 941AS ports are connected via cable to the 948? DOUT0 and DOUT1

Ans: Further investigation we see on Register 0x06 value as 0x68 which is DES Address. What does that mean?

2. If you have ALP installed, you can use it to set a test pattern output. This would generate a pattern internally from the 941AS and output to the 948. You can also change the PCLK rates, so that for testing purposes you can verify that a PCLK less than 105 MHz is working with single-link mode. Let me know if you have any questions about using ALP for the pattern generation.

Ans: We don’t have the TI eval HW, Instead we have an APTIV HW. With that how do we connect the ALP ? If you have any steps or video please provide?

3. Also we tried to do a pattern generation with below steps, but could not see anything on display

 i2cset -y 10 0xc 0x01 0x08 b  -- Disable DSI

i2cset -y 10 0xc 0x65 0x03 b  -- Pattern select

i2cset -y 10 0xc 0x64 0x11 b  -- Enable Pattern generator

i2cset -y 10 0xc 0x01 0x00 b  – Enable DSI

 below is the i2c dump we got after above pattern generation experiment

root@ospux-v920:~# i2cdump -f -y 10 0xc
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 92 00 00 68 00 00 01 8a 00 36 31 00 00    ?..?..h..??.61..
10: 26 00 5c 8b 00 00 01 1e 7f 7f 01 00 00 00 01 00    &.\?..?????...?.
20: 80 07 00 00 38 00 00 00 01 20 20 a0 20 00 a5 5a    ??..8...?  ? .?Z
30: 0a 00 00 05 50 00 1b 00 30 00 03 00 00 00 81 02    ?..?P.?.0.?...??
40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
50: 16 00 00 00 02 00 00 02 00 00 09 00 07 06 44 8c    ?...?..?..?.??D?
60: 22 02 00 00 11 03 00 00 00 00 00 00 00 00 20 00    "?..??........ .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 82 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 50 00 00 44 40 00 00 00 00 02 ff 00    ..?.P..D@....?..
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 40 08 00 00 00 00 00 00 00 02 00 00    ..?.@?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
root@ospux-v920:~#

4. How to verify pattern generator is enabled?

5. Unfortunately, all the tries we did, resulted in “Cable link not detected” in 0xc register. Is this the primary reason for display not coming up? Could you also suggest main debugging points and options which we can try?

Hi Rajesh,

1. The 0x6 register shows the DES ID correctly. Meaning it did detect the DES here.
0xC status register shows no valid PCLK input. This would be required from the DSI source to get LOCK.

**With your controller connected to the 941AS, can you read 0x68 (8-bit address for DES) register 0x0?

**Can you please check the LOCK pin on the 948 by probing it with an oscilloscope. Is LOCK always low or turns high?

2. **Here's a link to the ALP tool: https://www.ti.com/tool/ALP

After installing, you can connect your PC via Aardvark to the I2C lines on the 941AS (if you have access on board). You would have to choose the Aardvark as source, and setup for the 941AS device on the USB2ANY/Aardvark Setup menu.


3. **Please give me 1-2 days to send you a script to run for this. I will include the clock settings, pattern generation etc to get it running.

4. From the pattern generator 0x64-0x65 registers


5. **Can you please check whether the cable is dual or single link? 

The Ser-Des can work both single and dual link modes, but the video PCLK rates and FPD-link rates are different.

Datasheet states that: 
– Single link: up to 105MHz pixel clock
– Dual link: up to 210MHz pixel clock"





Best regards,
Ikram

Hi Ikram,

we are able to establish Link with the Deserializer and also detect the devices connected. Please find the I2C dump for the same.

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef

00: 18 00 00 1a 00 00 68 00 00 01 06 00 07 30 00 00 ?..?..h..??.?0..

10: 00 00 00 8b 00 00 fe 9e 7f 7f 01 00 00 00 01 00 ...?..?????...?.

20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a ?.%.....? ?..?Z

30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02 .?.??.........??

40: 04 21 60 00 00 00 00 00 00 00 00 00 00 00 00 8c ?!`............?

50: 16 00 00 00 02 00 00 02 00 00 c9 03 07 06 44 8b ?...?..?..????D?

60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 "?..?......... .

70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 82 00 ..............?.

80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

We are able to display with Pattern generator with 0x65  -- > 0x05 and 0x64 --> 0x01

when we run our application, we see blank screen and also observe DES_ERROR error is set

if we run the pattern generator with 0x65 --> 00 and 0x64 0x01 we observe blank screen. Please advise what could be wrong and further steps to debug.

Hi Rajesh,

Please look at this app note:https://www.ti.com/lit/an/snla132g/snla132g.pdf

It tells you how to set the registers for PatGen, including internal oscillator for PCLK, and display timing parameters (Htotal, Hactive, blanking, etc).
It looks like you are getting DES_ERROR because of CRC errors (0n 0xA register) and it's possible your lock is not continuous, although it does detect the DES. This could be because of the PCLK rate.


1.Change the clock rate:

Use 0x66 and 0x67 registers to set the indirect PatGen registers.

A. 160 MHz( will work only with dual-link):
- write PatGen register 0x3 = 0x14
- write PatGen register 0x3 = 0x04
- enable PatGeN using main page registers
- probe lock pin on 948 to check continuous lock

B. 160 MHz( will work only with dual-link):
- write PatGen register 0x3 = 0x14
- write PatGen register 0x3 = 0x02
- enable PatGeN using main page registers
- probe lock pin on 948 to check continuous lock


2. Can you please tell me whether you are using single or dual-link? This is important because the PCLK rate is limited by which you are using. I also shared the image on last response.


Thank you Rajesh. Let me know if this works. If needed we could also set up a call to work on this live.

Best regards,
Ikram

Can we setup a teams call today? Please let us know your availability.

We are using dual link lock

Hi Rajesh, please add me and then I will message you my email so we can set up a call.


Prior to meeting:
- Did you try the steps I shared in the last reply? It should allow you to get continuous LOCK and no CRC errors.
- For getting consistent display output you would need to program the PatGen indirect registers so that you can get. Please have the display timings ready
- please download ALP and see if you have an Aardvark to connect your PC/laptop to the 941AS on board. A TI EVM will also work.

Best regards,
Ikram