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DS80PCI800: Improvement of eye diagram by processing MIPI signal using DS80PCI800 chip

?? ?
Prodigy 10 points
Part Number: DS80PCI800
Other Parts Discussed in Thread: DS80PCI402, SN65DPHY440SS

Tool/software:

Hello, for the DS80PCI800 chip I have some questions, please answer, thank you!

1. I would like to ask how to determine the chip DS80PCI800 is 4 lane, I understand that the lane is the same time, including TX and RX two sets of data, looked at some of the schematic design of this chip found that the input and output are generally TX or are RX, so there are some questions in this regard!

2. If you want to process the MIPI signal, how to determine whether it should be set to GEN1, GEN2 or GEN3

3. The chip's power supply mode has 3.3V and 2.5V, the selection of these two modes of reference standards?

4. Due to the design requirements, it may be necessary to use 5V voltage through the level conversion chip to get the required voltage, the level conversion chip specifications and PCB layout requirements?

Translated with DeepL.com (free version)

  • 0
    TI__Mastermind 27950 points

    Hi,

    1. DS80PCI800 has a total of 8 channels oriented in the same direction. For TI parts, one channel refers to one differential pair oriented in one direction, while one lane refers to 2 differential pairs oriented in both directions. A 4 lane alternative would be DS80PCI402.

    2. DS80PCI800 isn't really intended to be used with MIPI signals. Its intended use case is PCIe Gen1, Gen2, and Gen3. Can you share the specific MIPI protocol/generation you are using?

    3. Yes, DS80PCI800 can be powered with either 3.3V or 2.5V. The "Pin Configuration and Functions" section of the datasheet explains how to connect each pin for both supply modes.

    4. Yes, you can use a step-down converter to get a 3.3V or 2.5V supply from a 5V input.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Ok, thank you lucas
    The product we are using is a camera and the MIPI protocol used should be camera serial interface -2(CSI-2).The image below shows the MIPI signal that needs to be processed, our aim is to improve the MIPI signal between the SENSOR board and the main board using this chip
    There are two other questions
    1. The DS80PCI800 input is divided into A and B. Is there any difference between the two?
    2. how to deal with the input and output pins that are not in use?

  • 0 in reply to ?? ?
    TI__Mastermind 27950 points

    Hi,

    Thank you for your clarifications. What data rate will each channel be operating at?

    Functionally A channels and B channels are identical. I believe they were named this way because DS80PCI800 is very similar to DS80PCI402, which orients B channels in the opposite direction of A channels.

    Unused channels can be powered off using SMBus register settings. The input/output pins can be left floating or tied to GND.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Mastermind 38965 points

    Hey,

    Can you confirm the number of CSI lanes you are using?

    We have the SN65DPHY440SS which is resigned as a CSI/ DSI retimer that will work for your application, but it only supports 4 data lanes and 1 clock. 

    This may be a better device to use.

  • 0 in reply to Vishesh Pithadiya
    Prodigy 10 points

    Thanks for your advice, but I'm sure this chip isn't quite right for it

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Thank you for your answer.

    The data transfer rate is 2.3Gbps per channel.
    Another question, what does the Normal Operation on the RESERVED pin mean?

  • 0 in reply to ?? ?
    TI__Mastermind 27950 points

    Hi,

    I understand, DPHY440SS supports a max data rate of 1.5 Gbps per channel so I cannot be used for your application. I'm checking with a CSI-2 expert on my team if anything else needs to be considered to use DS80PCI800 with CSI-2. I'll follow up when I have more feedback.

    TI marks pins or settings as "Reserved" when the functionality is kept internal. Pin 23 needs to be left floating for the redriver to operate correctly. Pin 21 should not be pulled to VDD because this is not a valid RATE setting.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Mastermind 27950 points

    Hi,

    After discussing your use case with a CSI-2 expert on my team, we came to the conclusion that we do not have a redriver which can support your use case.

    CSI-2 is based on the MIPI DPHY. DPHY has both high-speed (400mVppd) and low-speed (1.2V single-ended) signals. Our redrivers can't support the low-speed signaling. DPHY440 is the only device we have that can support both HS and LS, however it cannot support 2.3 Gbps per channel data rate. Therefore we do not have any device which can support this use case.

    Best,

    Lucas