SN65DPHY440SS: SN65DPHY440SS:

Hey Vishal,

where are these eye measurements taken in the block diagram?

We typically do not see close to a 650m application is this a typo? If the application is 650m insertion loss would play a huge role in the eye diagram, so I want to confirm where these measurements are taken.

Hi Vishesh

As i have mentioned in image itself first image is taken before MIPI Retimer Board and seconf waveform is taken after MIPI Retimer Board

what is the current setup of the device? (what are the control pins set to/ what is the I2C setup)

- is the EQ already maximized?

- do you have a schematic you can provide?

vishal prajapati said:

As i have mentioned in image itself first image is taken before MIPI Retimer Board and seconf waveform is taken after MIPI Retimer Board

Sorry I missed that in the original post. To better clarify my question. What do the TX and RX traces look like/ what are the insertion losses on the board that the DPHY440SS has to compensate for?

vishal prajapati said:

Also, observed that the MIPI clock datarate after retimer is changing from the original 890Mbps to 1.9Mbps.

The Data rate is 2x the clock rate which is why max data rate of data lanes is 1.5GBPS, but the maximum clock speed is 750MHz.

If the clock speed is over the 750MHz, then the PLL cannot properly lock onto the signal.

What is the frequency of the clock signal?

vishal prajapati said:

Also, observed that the MIPI clock datarate after retimer is changing from the original 890Mbps to 1.9Mbps.

This is most likely an error from the scope due to the improper eye. The period of differential signaling roughly the same across both images:

Hi Vishesh,

It is tested with differential probe which is soldered at the MIPI pins directly and I can see the major difference between the eye diagram. Also, It is failing with Mask recommended settings after retimer.

Vishesh Pithadiya said:

what is the current setup of the device? (what are the control pins set to/ what is the I2C setup)

The currently we are using R&S 16GHz oscilloscope and its differential probe for the MIPI 891Mbps speed for both the MIPI groups (two cameras in the system) so it is within the limit of Retimer.
Also, we are using the default hardware settings for the Retimer which get better results than the other tried multiple Retimer configurations, please find the schematic,

Vishesh Pithadiya said:

- is the EQ already maximized?

What settings we need to do ? Currently it is pulled up on the Hardware side due to SCL pin.

Vishesh Pithadiya said:

- do you have a schematic you can provide?

Provided image above

Vishesh Pithadiya said:

What is the frequency of the clock signal?

89Mbps for both camera so around 445MHz clock,

Also, Currently Retimer is placed in the middle as per earlier shared block diagram in the original first post which will have around 400mm distance from Camera board and more 350mm distance will be after retimer to processor board. so on basis please share the best register configuration settings considering this received waveforms. 

We are stuck on the project due to this and your prompt response is highly apprecialted with solution.

Hey Nilav,

Are you able to send the layout of the board as well. I'm trying to understand what is causing the bad eye. I haven't seen something like this before. 

I'm not sure what you're referring to by default settings. as the swing adjust and pre-emphasis are pulled high and low, creating a floating point for both these values in the schematic. 

I recommend using the following settings for Voltage Swing, HS Pre-emphasis, and LPTX Edge Rate Controls.

From the looks of the schematic you are using I2C to control the device. 

I recommend testing the effect of EQ on the signal. Can you capture waveforms using 0dB and 5dB EQ?

What is the width of the traces used in the board design. We recommend 10 mil width

Hi Vishesh,

I can't send the layout as it is client's proprietary but let me share you more details for layout routing,
Currenly MIPI signals are routed through Camera+MCU+Retimer+CCB boards and passing though the 50Ohm co-axial cable.
Also, we are using slipring (a mechanical part which has 26AWG teflon cable on both side of mechanical arrangements)
Camera board: (Yellow highlighted) 85Ohm (L1/L3: 5.2/4.5mils)

MCU Layout: (Yellow highlighted) 85Ohm (L1/L3: 5.5/5.5mils)


Retimer board:(Yellow highlighted) 85Ohm (L1/L3: 5.5/5.5mils)

Ok, we will test with your shared settings for Voltage Swing, HS Pre-emphasis, and LPTX Edge Rate Controls.

We have already tested EQ with 0 and 5 dB and observed stuck in both cases and not observed major changes in stuck from 0 to 5dB. What should be other register settings at that time.

PS: The default retimer configuration means no register settings from firmware.

Kindly suggest the best configutation to resolve the streaming stuck issue as we are stuck in the project due to this issue.

Thanks & Regards,
Nilav Choksi

Hey Nilav,

I'm trying to see what would cause the device eye to be so poor. It seems like this isn't simply an EQ of pre-emphasis configuration problem. The traces shown are thinner than the than recommended and this would affect insertion loss, but at 445MHz this would not effect the eye to this extent. Are you following the proper transitions from the LP11 state to the HS state?

Try setting lane 0 to the HS state using the following commands and see if that improves the eye for lane 0:

Enable HS path for Lane 0 only:

Write Register 0x50 with 8’h01 //Override enable for HS TX path

Write Register 0x51 with 8’h01 //HS TX path enabled.

Write Register 0x61 with 8’h00  // Disable LP path.

Write Register 0x70 with 8’h01  //Override enable for HS RX path

Write Register 0x71 with 8’h01  // HS RX path enabled.

If this improves the eye. I will speak to the designers and see if I am able to get the commands that will force all the lanes into HS mode. 

Hi Vishesh, 

We tried your configuration provided for HS path as below but after updating these registers, we are not able to get camera stream and stream is stopped.

Write Register 0x50 with 8’h01 //Override enable for HS TX path

Write Register 0x51 with 8’h01 //HS TX path enabled.

Write Register 0x61 with 8’h00  // Disable LP path.

Write Register 0x70 with 8’h01  //Override enable for HS RX path

Write Register 0x71 with 8’h01  // HS RX path enabled.

After writing all the above registers, we read the registers again and we are getting some different values on 0x51 and 0x71 registers. 

Read values after writing above registers : 

On register 0x51, we are getting 0x11 value.

On register 0x71, we are getting 0x1F value

Hi Eiffel,

Are you writing these register values while there is data coming, or are you configuring the device before data is being transmitted?

In this case, forcing HS state means the is device will not be able to pass LP signaling across. This LP signaling is required to setup the transmitter of the MIPI source to HS state. If we change the device to HS state before the MIPI source is not configured for HS state this may cause breakdown. If not already done, try changing this register value as HS data is being sent across the lane. 

Also can you verify the proper steps are taking place between the MIPI lines on the MUCU board and the retimer board to place the retimer in HS mode?

Also does this occur across multiple boards and devices? Have you tried an ABA swap with the device?

The retimer is connected to the MCU, while the camera streaming is handled by the processor. Since the MCU doesn't know when the streaming starts, we can't configure the retimer each time streaming begins or ends. Instead, we're configuring the retimer only once, during the MCU reset.

Additionally, I'm not sure that why we need to manually set the HS mode. This isn't mentioned in the datasheet, and the register settings you shared also don't seem to be documented there. Based on my understanding, this should be handled automatically by the IC, with only EQ and voltage settings needing manual configuration.

Another update: when we replaced the slip ring with cables, the MIPI lines showed the correct EYE diagram, even without configuring the HS line registers.

Hey Eiffel,

This is great news! What are the differences between the slip ring you are using and the traditional cables? 

The reason we may need to set the lane into HS mode is due to the fact that lane 0 is also used for bac communication using the DSI protocol. 

In the case where this back-communication is not required (CSI interface), then sometimes its advantageous to force this lane in HS mode. This works when you have a processor between the MIPI source and sink which may not properly send the LP signal across to configure the SN65DPHY440SS. 

Hi VIshesh,

We have just bypass the slip ring mechanism and used direct cables for connections.

But still we want to configure retimer to check different Eye diagram with slip ring.

In our setup Micro controller is connected with retimer and it is independent of MIPI lines and never knows when the data transmitted and recieved.

Whatever you are suggesting for HS mode configuration for registers are not mentioned in datasheet. 

Can you please help to configure registers from datasheet. 

Hey Eiffel,

These registers I provided are used to bypass the internal auto config, this is not in the datasheet as this is bypassing some of our internal logic block which is not recommended .

It seems that the DPHY440SS is being configured correctly, but we seeing odd terminations when using the slipring.

Are you able to use a TDR to test the impendence of the slipring?