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DS160PR412: DS160PR412, 421 use in mixed PCIe G2 and USB 3.1 applications

Part Number: DS160PR412
Other Parts Discussed in Thread: HD3SS3220, , DS160PR421, SN75LVPE5412

Tool/software:

These are my first steps in this type of circuits and I would really appreciate the opinion of an expert:

The big caption:

I'm using a ALTERA CYCLONE 10 GX FPGA, and I need to multiplex 4 FPGA transceivers (12.5 Gbps capable) in two applications to be dynamically selected:

> In USE1, the four transceivers will support a short range connection to a Solid State disk, using a 4-lane PCIe Gen2 interface at 5Gbps.
> In USE2, the four transceivers will be assigned to support one USB3.1 port, one SFP+10G optical link, and two inter-board links (still TBD). For the USB 3.1 front end, I selected TI's HD3SS3220 10-Gbps USB 3.1 Type-C 2:1 mux with DRP Controller.

Now, my question:

As for the quad 2:1 mux/demux to put between the HD3SS3220 and the FPGA, I have planned to use the TI's DS160PR412/421 pair to switch and redrive between 4-lane PCIe (in USE 1), and USB 3.1 plus SFP+ plus 2TBD (in USE 2). Since the DS160PR412/421 and the HD3SS3220 gain and EQ behavior can be dynamically programmed via I2C I assumed that the above set could be used for this purpose.

Is this correct, am I missing some essential thing or am I making a big mistake?

Thank you very much

Guillermo

  • Hi Guillermo,

    I'm a bit confused about your setup. Can you clarify a few points? I'd like to have a better understanding before I make any recommendations.

    1. Are the same 4 transceivers being used to support PCIe Gen2 or USB 3.1/SFP+ 10G/TBD? Or are there 8 transceivers total which need to be muxed/demuxed between for each use case?
    2. Does each transceiver include 4 lanes total?
    3. Are the same Altera FPGA ports being used in both use cases? Or is mux/demux necessary to route the signals to PCIe Gen2 ports versus USB 3.1/10G/TBD ports?
    4. What is the HD3SS3220 being used to mux between? Can you share what the inputs and outputs are?
    5. Can you share a block diagram for my understanding?

    Best,

    Lucas

  • Hi Lucas

    I hope the attached diagram will explain better my objectives.

    I have only 4 FPGA transceivers available

    DS160PR412/421 will work as quad 2:1 muxes/demuxes, the DS160PR412 for the TX channels and the DS160PR421 for the RX channels, to select between USE1 or USE2

    In USE1 the 4 selected Tx/Rx channels will be use to support the USB3.1 (Gen1, 5 Gbps), SFP+ (10 Gbps), and 2TBD connections

    In USE2 the 4 selected Tx/Rx channels will be used to support one 4.Lane PCIe G2 interface, running at 5 Gbps/lane

    The HS3SS3220 is needed for the USB3.1 interface to tolerate connector rotation

    I hope the image will show my idea.

    Basically, DS160PR412/421 are shown as high speed mux & redrivers, they are mentioned as useful for PCIe mux/demuxing, but not for USB mux/demux, so I asked for an expert opinjon why not. I suppose that having I2C interfaces, Gain and EQ can be modified when we change between USE1 and USE2.

    Regards

    Guillermo

  • Hi Guillermo,

    Thank you for sharing this block diagram, I now have a much better understanding of your setup.

    Yes, DS160PR412/421 can be used in this system to switch between PCIe Gen4 and USB3.1/10G SFP+/TBD use cases. There are a few caveats which you should consider.

    1. DS160PR412/421 equalization is targeted for 16 Gbps. Gain at lower rates (10.3125 Gbps or 5 Gbps) will not be as high.
    2. DS160PR412/421 is targeted for PCIe and thus it has RX-detect. Meaning it is expecting to see termination on its output before it turns on termination on its own input. RX-detect will need to be disabled for USB and Ethernet use cases. This is possible through pin or register control.
    3. DS160PR412/421 is designed to support data rates up to 16 Gbps. If higher rates are necessary for TBD use cases, we additionally have SN75LVPE5412/421 redriver mux/demux. This is a very similar part which supports up to 32 Gbps.

    Best,

    Lucas