DS90UB954-Q1: Test Pattern generation settings for RAW10 format

Rafeeq SM

Part Number: DS90UB954-Q1

Tool/software:

I'm looking for the correct settings for the Test pattern generation to mimic my sensor, inorder to check my circuitry without the sensor. The specification is as follows, and I made the register setting as follows but there is no image for my reception FPGA. Please hlep me to correct the settings, thank you…

>> RAW10, 800x800, 4 lane configuration with 200 Mbps per Lane speed

>> DS90UB954 REFCLK is 25MHz

>> DS90UB954 Mode PIN is selected CSI-2 Non Synchronous Back Channel

//Patgen Fixed Colorbar 800x800

{0x33,0x01}, // CSI0 enable

{0xB0,0x00}, // Indirect Pattern Gen Registers

{0xB1,0x01}, // PGEN_CTL /* Enable Pattern Generator */

{0xB2,0x01},

{0xB1,0x02}, // PGEN_CFG /* 8 color 5 block Pattern Generator */

{0xB2,0x35},

{0xB1,0x03}, // PGEN_CSI_DI RAW10

{0xB2,0x2B},

{0xB1,0x04}, // PGEN_LINE_SIZE1

{0xB2,0x0F},

{0xB1,0x05}, // PGEN_LINE_SIZE0

{0xB2,0xA0},

{0xB1,0x06}, // PGEN_BAR_SIZE1

{0xB2,0x00},

{0xB1,0x07}, // PGEN_BAR_SIZE0

{0xB2,0x7D},

{0xB1,0x08}, // PGEN_ACT_LPF1 for 800 pixel its 1000(0x03)

{0xB2,0x03},

{0xB1,0x09}, // PGEN_ACT_LPF0 for 800 pixel its 1000(0x20)

{0xB2,0x20},

{0xB1,0x0A}, // PGEN_TOT_LPF1 for 960 pixel its 1000(0x03)

{0xB2,0x03},

{0xB1,0x0B}, // PGEN_TOT_LPF0 for 960 pixel its 1000(0x03)

{0xB2,0xC0},

{0xB1,0x0C}, // PGEN_LINE_PD1

{0xB2,0x0C},

{0xB1,0x0D}, // PGEN_LINE_PD0

{0xB2,0x67},

{0xB1,0x0D}, // PGEN_VBP

{0xB2,0x21},

{0xB1,0x0F}, // PGEN_VFP

{0xB2,0x13}

11 months ago

0 Hamzeh Jaradat 11 months ago

TI__Guru** 108100 points

Hello Rafeeq,

Can you provide more details about your video signal? I need:

Number of frames per second, H-active, H-total, V-active, V-back porch, V-front porch, V-synch width.

0 Rafeeq SM 11 months ago in reply to Hamzeh Jaradat

Prodigy 140 points

Hi Hamzeh,

I'm still waiting for the sensor vendor for those information, I'll get back to you once I got those data. Thank you...

0 Hamzeh Jaradat 11 months ago in reply to Rafeeq SM

TI__Guru** 108100 points

Hi Rafeeq,

thanks for the info. Whenever you have the details, just post them and I will response.

0 Rafeeq SM 11 months ago in reply to Hamzeh Jaradat

Prodigy 140 points

Hi Hamzah,

H-active = 1280, Htotal = 744(depends on clock freq), V-active = 800, Vback& Vfront poorch is not present in their CSI2 sensor output, also Vsyns

0 Hamzeh Jaradat 11 months ago in reply to Rafeeq SM

TI__Guru** 108100 points

Hi Rafeeq,

not sure if there is a typo in the provided info. You said, H-active = 1280, Htotal = 744 !! That is not possible. Htotal must be larger than Hactive.

0 Rafeeq SM 11 months ago in reply to Hamzeh Jaradat

Prodigy 140 points

Hi Hamzeh,

You are right the data is confusing, I obtained this from the sensor datasheet. Please find below the datasheet snippets. The actual sensor output is 800x800 RAW10, CSI-2 lane @ 400 Mbps per lane. I want to replicate this resolution to test the link with the test pattern generator output from both the deserialiser. I made a settings with some standard values, so can you confirm the settings is correct as I'm getting around 16fps, instead of 30fps. Thank you...

{0x1F,0x03}, // CSI0 400Mbps serial rate

{0x33,0x21}, // CSI0 enable, 2 Lanes, CSI non continuous clock mode

{0xB0,0x00}, // Indirect access (Write = 0x00, Read = 0x01)to Pattern Gen Registers

{0xB1,0x01}, // PGEN_CTL /* Enable Pattern Generator */

{0xB2,0x01},

{0xB1,0x02}, // PGEN_CFG /* 8 color 5 block Pattern Generator */

{0xB2,0x35},

{0xB1,0x03}, // PGEN_CSI_DI RAW10

{0xB2,0x2B},

{0xB1,0x04}, // PGEN_LINE_SIZE1

{0xB2,0x0F},

{0xB1,0x05}, // PGEN_LINE_SIZE0

{0xB2,0xA0},

{0xB1,0x06}, // PGEN_BAR_SIZE1

{0xB2,0x00},

{0xB1,0x07}, // PGEN_BAR_SIZE0

{0xB2,0x7D},

{0xB1,0x08}, // PGEN_ACT_LPF1

{0xB2,0x03},

{0xB1,0x09}, // PGEN_ACT_LPF0

{0xB2,0x20},

{0xB1,0x0A}, // PGEN_TOT_LPF1

{0xB2,0x03},

{0xB1,0x0B}, // PGEN_TOT_LPF0

{0xB2,0xC0},

{0xB1,0x0C}, // PGEN_LINE_PD1

{0xB2,0x0C},

{0xB1,0x0D}, // PGEN_LINE_PD0

{0xB2,0x67},

{0xB1,0x0D}, // PGEN_VBP

{0xB2,0x21},

{0xB1,0x0F}, // PGEN_VFP

{0xB2,0x13}

0 Hamzeh Jaradat 11 months ago in reply to Rafeeq SM

TI__Guru** 108100 points

Hello Rafeeq,

please try the following script.

{0x1F,0x03}, // CSI0 400Mbps serial rate

{0x33,0x21}, // CSI0 enable, 2 Lanes, CSI non continuous clock mode

{0xB0,0x00}, // Indirect access (Write = 0x00, Read = 0x01)to Pattern Gen Registers
{0xB1,0x01}, // PGEN_CTL /* Enable Pattern Generator */
{0xB2,0x01},

{0xB1,0x02}, // PGEN_CFG /* 8 color 5 block Pattern Generator */
{0xB2,0x35},

{0xB1,0x03}, // PGEN_CSI_DI RAW10
{0xB2,0x2B},

{0xB1,0x04}, // PGEN_LINE_SIZE1
{0xB2,0x03},

{0xB1,0x05}, // PGEN_LINE_SIZE0
{0xB2,0xE8},

{0xB1,0x06}, // PGEN_BAR_SIZE1
{0xB2,0x00},

{0xB1,0x07}, // PGEN_BAR_SIZE0
{0xB2,0x7D},

{0xB1,0x08}, // PGEN_ACT_LPF1
{0xB2,0x03},

{0xB1,0x09}, // PGEN_ACT_LPF0
{0xB2,0x20},

{0xB1,0x0A}, // PGEN_TOT_LPF1
{0xB2,0x03},

{0xB1,0x0B}, // PGEN_TOT_LPF0
{0xB2,0x4D},

{0xB1,0x0C}, // PGEN_LINE_PD1
{0xB2,0x0F},

{0xB1,0x0D}, // PGEN_LINE_PD0
{0xB2,0x69},

{0xB1,0x0D}, // PGEN_VBP
{0xB2,0x21},

{0xB1,0x0F}, // PGEN_VFP
{0xB2,0x0A}

{0xB1,0x10}
{0xB2, 0xAA}, // PGEN_COLOR0

{0xB1,0x11}
{0xB2,0x33}, // PGEN_COLOR1

{0xB1,0x12}	
{0xB2,0xF0}, // PGEN_COLOR2

{0xB1,0x13}	
{0xB2,0x7F}, // PGEN_COLOR3

{0xB1,0x14}	
{0xB2,0x55}, // PGEN_COLOR4

{0xB1,0x15}	
{0xB2,0xCC}, // PGEN_COLOR5

{0xB1,0x16}	
{0xB1,0x0F}, // PGEN_COLOR6

{0xB1,0x17}	
{0xB2,0x80}, // PGEN_COLOR7

{0xB1,0x18}	
{0xB2,0x00}, // PGEN_COLOR8

{0xB1,0x19}	
{0xB2,0x00}, // PGEN_COLOR9

{0xB1,0x1A}	
{0xB2,0x00}, // PGEN_COLOR10

{0xB1,0x1B}	
{0xB2,0x00}, // PGEN_COLOR11

{0xB1,0x1C}	
{0xB2,0x00}, // PGEN_COLOR12

{0xB1,0x1D}	
{0xB2,0x00}, // PGEN_COLOR13

{0xB1,0x1E}	
{0xB2,0x00}, // PGEN_COLOR14

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DS90UB954-Q1: Test Pattern generation settings for RAW10 format