Tool/software:
We have a DP83TG720S-Q1 PHY that is coming up in SGMII mode following a hardware reset. From U-Boot, register 0x45D (SOR_VECTOR_1) reads back as 0x2008, indicating
SGMII_EN=1, RGMII_EN=0, MAC_MODE=0x0=SGMII, PHY_AD=0x8
We need the PHY to operate in RGMII mode, though, and we believe the resistor strapping is set for that.
From U-Boot reading register 0x45d:
UBOOT> mii write 0x8 0xd 1f;
mii write 0x8 0xe 0x45d;
mii write 0x8 0xd 0x401f;
mii read 0x8 0xe
2008
We saw this forum post: DP83TG720R-Q1: MAC address and RGMII mode selection, pull-up resistor - Interface forum - Interface - TI E2E support forums
and attempted to follow the sequence there to put the PHY into RGMII mode from U-Boot:
gpio clear 21 # Assert PHY reset line
gpio set 21; # Deassert reset
# Clear bit 9 in 0x608 to disable SGMII
mii write 0x8 0xd 1f ;
mii write 0x8 0xe 0x608 ;
mii write 0x8 0xd 0x401f;
mii write 0x8 0xe 0x7b ;
# Set Bit 3 in 0x600 to enable RGMII
mii write 0x8 0xd 1f ;
mii write 0x8 0xe 0x600 ;
mii write 0x8 0xd 0x401f;
mii write 0x8 0xe 0x128
When we read these two registers back, they match what we wrote (0x7b and 0x128 respectively), but register 0x45d always reads back as 0x2008. I have also tried writing BMCR bit 15 to soft-reset the PHY after doing this and still see 0x2008 in 0x45d. Additionally, we do not see communications with the MAC and the PHY does still appear to be in SGMII mode.
The power supply rise time is well within the datasheet spec and we have confirmed that the RGMII lines are quiescent (high-impedance on the FPGA-side) when the PHY samples the strapping resistors. We've probed the RGMII lines with an oscilloscope and confirmed the PHY is clearly in SGMII mode.
Do you have any ideas on how to switch the PHY into RGMII mode or why it may be coming up in the wrong mode?
Thanks!
