This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

NS16C2752: MR Reset and Power-on Reset

Part Number: NS16C2752

Tool/software:

Hi,

I have any question.

1, When resetting by the MR pin, which timing is correct when/TXRDYx goes from High to Low?

     a) At the same time as resetting by the MR pin

     b) x sec after resetting by the MR pin. If there is a formula or specification for x sec, please tell me.

2, Which is correct about the relationship between power-on reset and MR reset?

    a) When both resets are released, IC releases reset.

    b) When one reset is released, IC releases reset.

3, What is the voltage threshold value at which power-on reset is released?

Best Regards,

Nishie

  • Hi Nishie,

    1, When resetting by the MR pin, which timing is correct when/TXRDYx goes from High to Low?

         a) At the same time as resetting by the MR pin

         b) x sec after resetting by the MR pin. If there is a formula or specification for x sec, please tell me.

    I'm actually not sure about this. My guess is it should occur within double digit nano seconds during the device being held in reset. 

    I don't have an EVM for this device. I would need to order the device and a breakout board to test to see if TXRDY would flip during the reset or some time after. Is this something you really need? This would probably take ~2 weeks for me to get the breakout board and set it up to test. 

    2, Which is correct about the relationship between power-on reset and MR reset?

        a) When both resets are released, IC releases reset.

        b) When one reset is released, IC releases reset.

    The answer should be a but I recommend you toggle reset after power up....

    The device should perform a reset when it powers up but I've heard sometimes (in general, just for this device specifically) if the power up Vcc ramp rate is bad (non-monotonic or too fast/slow) then the power on reset can sometimes doesn't work. My personal opinion is you should always toggle the reset pin after you power up just to be sure. 

    3, What is the voltage threshold value at which power-on reset is released?

    The datasheet recommends you hold the reset pin below 0.8V to ensure it sees a logic low and above ~2V or 2.2V (depends on Vcc) to ensure it sees a logic high. I would recommend you use these levels. 

    -Bobby

  • Hi Bobby-san,

    Thank you for your support!

    Best Regards,

    Nishie

  • Hi Bobby-san,

    Let me ask you an additional question.

    The device should perform a reset when it powers up but I've heard sometimes (in general, just for this device specifically) if the power up Vcc ramp rate is bad (non-monotonic or too fast/slow) then the power on reset can sometimes doesn't work.

    Is there an indication of the too fast/slow ramp rate of VCC? If you have Min and Max values, please let me know.

    Best Regards,

    Nishie

  • Is there an indication of the too fast/slow ramp rate of VCC? If you have Min and Max values, please let me know.

    What I've seen recommended in another datasheet for a digital device was 100uS minimum and 2 seconds maximum. Most customer's I see have a ramp rate in the double digit millisecond range. Rising/falling being measured from GND to Vcc. 

    In some system's I've seen power up ramp rate on Vcc sometimes does not start at GND which can cause problems as well. I would recommend you ramp from GND and not a voltage like 0.4V or 0.7V to Vcc.

    -Bobby