Tool/software:
I will be using 17 DP83867IS PHYs connected to a single FPGA. I will use SGMII and two MDI buses. I will use GbE.
I am currently looking into the CLK distribution. The datasheet states the following:
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal
clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input.
The default output clock is suitable for use as the reference clock of another DP83867 device.
What is the phase delay between the input CLK at XI and CLK_OUT? How many PHY CLKs can be connected in this daisy-chain fashion before the phase difference is too big? Is it possible to connect one 25MHz crystal to PHY 1 and then use its output for PHY 2, its output for PHY 3 and so on until PHY 17 (PHY 17's output will then be used as the FPGA reference clock)?
An alternative design is to use an oscillator IC with LVCMOS clock buffers/dividers to have all the clocks synchronous.
