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DP83561-SP: Power-on diagram clarification

Tijana Igic1
Prodigy 140 points
Part Number: DP83561-SP

Tool/software:

Hello, in figure 6-1 of the DP83561-SP datasheet, for the power up timing, is T1 with respect to the VDD rail coming up or with respect to clock edge?

We were not certain given the parameter description for T1 is last supply power rail ramp to RESET_N, but in the drawing, it appears to be going to the clock edge.

Is this assuming rails ramp up and stable clock provided followed by 200ms from the first stable clock edge?

 

Secondly, the T3 time for the straps to latch is specified only at nominal to 200ms. Is there a max time we should be waiting before attempting to use these dual pins?

Thank you!

  • 0
    TI__Mastermind 25955 points

    Hi Tijana,

    I think the datasheet might be confusing. The mean time we are referring to for T3 is the minimum time we need to wait after power up for the Dual pins enable. There is no requirement for the maximum waiting time after power up.

    --

    Regards,

    Hillman Lin