Tool/software:
Hello, in figure 6-1 of the DP83561-SP datasheet, for the power up timing, is T1 with respect to the VDD rail coming up or with respect to clock edge?
We were not certain given the parameter description for T1 is last supply power rail ramp to RESET_N, but in the drawing, it appears to be going to the clock edge.
Is this assuming rails ramp up and stable clock provided followed by 200ms from the first stable clock edge?
Secondly, the T3 time for the straps to latch is specified only at nominal to 200ms. Is there a max time we should be waiting before attempting to use these dual pins?
Thank you!