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DP83869HM: MDIO reads are returning invalid register values

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Tool/software:

I have a custom board with a microprocessor connected to the DP83869HM and when I perform MDIO bus transactions I get invalid responses. After physical toggling the reset on the PHY I initialize the ETH driver on my hardware and read back 0x9815, 0x9055, or 0x9855 from registers 2 and 3 which contain the OUI. I modified to read the first 32 registers and they all return this value except for register 0xd and 0xe which return 0.

If I remove and remount the module this is persistent across a power cycle, for example I'll always receive 0x9815. If I reset just the PHY the number remains persistent. If I do a complete system power cycle then the return value may change to one of the others listed above. It is pretty inconsistent.

We hooked up a logic analyzer to the MDIO/MDC pins and verified that this is what we are seeing on there as well as through printk statements placed within the Linux MDIO subsystem. 

Is there something physical that could cause this? The signals look very clean and it is certainly returning these values, I just can't figure out why.

  • Hi Jason,

    Based on your summary. The issue most likely occur on software side.

    One thing we would like to check is making sure is to have pull up resistor on MDIO lines.

    --

    Regards,

    Hillman Lin

  • Hi Hillman,

    We do have pull up resistors on the MDIO lines. I'm not sure how it would be a software problem when we are just initially probing the actual MDIO bus. Here is a diagram showing a requested read to the PHY from the processor.



    The timing diagram in the DP83869 datasheet indicates that the PHY puts its data on the MDIO bus relative to the rising edge of MDC with 0 to 10ns of output delay. Can you confirm that this data timing is relative to the MDC rising edge? Our processor is putting data out relative to the falling edge of the clock and this is centering the sampling nicely for the PHY with ample setup and hold time margin.

  • Hi Jason,

    Based on the logic analyzer, It seems like the MDIO bus is operate as expected.

    This is most likely due to the software not recognizing the correct PHY ID. May I ask what is the block diagram in your system? or which device is connected on MDIO bus?

    --

    Regards,

    Hillman Lin

  • We are using an NXP S32G3 processor to connect to the PHY. We are expecting to get back 0x2000 per the DP datasheet but are seeing other values being returned. 

    We have tried just iterating over all the possibly PHYs in the system (0-15) addressed but noone else returns anything but 0xFFFF.

  • Problem was RBIAS was not pulled to ground correctly.