TCAN4550: configuration questions

Hello Well,

You are not required to use the interrupts, so this is completely your choice and preference.

Register 0x000C informs about errors with the SPI interface.  Additional information on the reason for the error is found by reading register 0x0010.  The devices uses a FIFO on the SPI interface to handle the clock domain crossing between the SPI clock and the digital clock domain (OSC1/2 clock). 

SPI data is loaded into the FIFO based on the SPI clock and pulled out of the FIFO from the OSC clock on a SPI Write transaction.

Likewise, the digital core loads data into the FIFO on the OSC clock and the MCU pulls the data out of the FIFO with the SPI clock on a SPI Read transaction.

To monitor and check for errors, the device keeps track of the number of clock cycles and bits in the FIFO to ensure there is the exact number for each transaction and sets an error if there are too many clock cycles, or too many bits corresponding to an incorrect "Length" field value.  For example, if the Length field is set to "1", then there should only be 32 data bits.  If the Length field is set to 2, then there should be 64 data bits.  Too many or too few bits can result in an overflow or underflow error. and will then set the appropriate status flag bits.

Any clock related issues or disruptions to the clocks will also cause errors in the SPI FIFO.  Please also be aware of and review the TCAN455x Clock Optimization and Design Guidelines application report (Link) when optimizing the clock circuit for your design to ensure it is stable.

In register 0x0820, the VTWD bit is set because of the ECCERR (bit 16) is set and the SPIERR bit is set indicating some form of error has occurred in the SPI communication.  The GLOBALERR bit is set when any other bit is set.  For the ECC Error, this could occur if the MRAM has not been cleared properly, but also reading the Test Register 0x080C can provide additional information.

For register 0x0824, the TSW bit is set which is not an error but an indication that the used to generate the CAN message Time Stamp (if used) has wrapped around to the beginning.  However, the Protocol Error in Arbitration Phase (PEA) bit is set which usually indicates there is an error with the CAN bus configuration parameters such as the Nominal Bit Timing parameters resulting in other CAN nodes not properly being able to process messages during the arbitration phase.  Poor signal integrity on the CAN bus can also lead to bit sampling errors during this phase of the message and lead to errors.  But assuming the signal integrity is good, you should verify that the bit timing configuration settings are identical to all other nodes on your CAN bus to avoid any errors.

Regards,

Jonathan