Tool/software:
Hi,
We are facing an issue with our design involving the DP83867I PHY. The nINT/nPWRDN pin is connected to the processor's CCM_CLK signal, which initially functions as a clock but is later reconfigured to a GPIO. Here are the specifics:
- Connection: The nINT/nPWRDN pin of the DP83867I is connected to the processor's CCM_CLK0 signal.
- Behavior: At reset, the CCM_CLK0 pin outputs a clock signal for approximately 20ms after nRESET_OUT is asserted. After this period, we change the function of CCM_CLK0 to act as a GPIO for our application.
- Problem: During reset, while the nINT/nPWRDN pin is in nPWRDN mode, it is exposed to the clock signal from CCM_CLK0. After reset, we reconfigure CCM_CLK0 as a GPIO and switch the nINT/nPWRDN pin to function as an interrupt.
- Concern: We are worried that the clock signal at reset could cause issues with the PHY’s power-down function or interfere when the pin is later switched to interrupt mode.
Could this clock signal cause any problems with the PHY’s behavior, especially during the reset phase or when transitioning the nINT/nPWRDN pin to interrupt mode? Is there a recommended way to mitigate any potential issues caused by the clock signal?
Any insights or guidance would be greatly appreciated!
Thank you for your help!
