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DP83867IS: Query on the power on sequencing

Ariharan S
Prodigy 80 points

Part Number: DP83867IS

Tool/software:

Hi,

During the power-on sequence, Before supplying VDDIO (1.8V) for the DP83867ISRGZR. We plan to supply the stable LVCMOS1V8 25MHz +/-50ppm clock from an on-board oscillator. However, VDD1P0 (1V) and VDDA2P5 (2.5V) will be applied before the clock starts to toggle.

Does this momentary hot-socketing during the power-on sequence is allowed? As per the "Figure 6-1. Power-Up Timing" of the Datasheet we believe it is supported.

Also, we believe, our two supply schemes wouldn't need any sequencing between rails.

Kindly confirm the above queries at the earliest. 

 

  • 0
    TI__Mastermind 19621 points

    Hi Ariharan,

    I believe this would cause some issues, we normally want the Clock to be stable before the Power Supplies ramp up. If the Power Supply Sequence cannot be altered, I would recommend holding the PHY in a Pin RESET until the clock is stable, releasing it from RESET after the stable clock will guarantee the PHY boots up as expected.

    Regards,

    Alvaro