Other Parts Discussed in Thread: USB-2-MDIO
Tool/software:
Hello,
We are using the DP83826I with a Soft-MAC in an Spartan-7 FPGA and experience sporadic packet receive errors. Occasionally, the MAC receives only the first part of a 551 byte packet. The previous and subsequent packet are received in full. We only see errors in the receive direction and only when we are simultaneously transmitting traffic (192 byte packets every 3ms). If we stop transmissions, all packets are received in full.
The RX traffic comes from an embedded switch on a separate board via a board2board connection.
We believe this traffic is good (see details below), but the PHY does not report any errors, low link quality or the like when it forwards a truncated packet to the MAC (which then obviously raises a CRC error).
Is there a good explanation we have overlooked that can explain this behaviour in the PHY?
More details:
The PHY is MII Master and we use fixed-link 100Mbit full-duplex.
On the MDI side, there is a board2board connection to a main board with an embedded Marvel Switch (mv88e6290).
┌────────────────┐ ┌────────────────────┐
│ CPU <-> Switch │ <- Board2Board -> │ PHY <-> FPGA w/MAC │
└────────────────┘ connector └────────────────────┘
Our understanding is that the RX_DV signal shows the period when the data is valid on the 25Mhz MII interface, and from examining the length of this signal being asserted, we see that the PHY sends too short a packet to the MAC. The number of bytes sent when the error occurs is not constant (we have seen anything from 120-something bytes to 500-something).
We have been examining the PHY status registers and found no sign of errors being reported by the PHY:
- Good link Quality, even when error occurs: MSE_Val (reg 0218h): less than 0030h (48).
- No Receive Errors (RX_ER line never asserted, RECR = 0, ReceiveErrorLatch in PHYSTS is 0)
- No change in Link Quality, Status etc. (MISR1=0)
- No Remote Fault, Descrambler Lock is active, Signal Detected, No False Carrier occurred (PHYSTS = 0605)
The fact that the error only happens when also transmitting had us thinking that we may have a noise/crosstalk problem, but then we would expect to see some full packets received with bit errors (reported as CRC errors in the MAC). We have not seen that, only short packets in the RX direction.
Also, if there was an error on receiving the symbols on the MDI side of the PHY, we would expect to see link errors or receive errors. Neither of those are seen either.
As we cannot easily analyze the signals on the Board2Board connection directly, we use a small debug interface board, which we can connect instead of the FPGA board and allows us to run the data to software on a PC, thereby simulating the FPGA functionality:
┌────────────────┐ ┌─────────────────┐ ┌────────────────┐
│ CPU <-> Switch │ <- Board2Board -> │ Interface Board │ <- Cat5e -> │ PC w/ FPGA sim │
└────────────────┘ connector │ w/RJ-45 │ └────────────────┘
└─────────────────┘
We do not see any errors when using this setup (FPGA sim also simulates the TX traffic), so we believe the data sent by the embedded switch on the CPU board is ok.
On a side note:
Curiously, we see RX FIFO Overflow (RCSR = 0x41) being asserted when no ethernet traffic is flowing through the PHY. When we enable traffic (regardless of the direction being RX or TX), the overflow status is de-asserted after a short while. The Overflow assertion does not seem to be linked to the receive errors we see, but we are not sure what to make of this assertion, since our PHY is MII Master.
What would make the PHY assert the RX FIFO overflow when in Master mode?
Best regards,
Mikael
