SN65DSI86-Q1: REFCLK tolerance

Hi,

I am looking into this and asking the relevant engineers. I will follow up as soon as I have an answer

Hi,

Sorry no update yet. I have sent a follow-up.

Hi,

Just got the update. The DSI86 will be able to latch onto the incoming signal but this will affect the DP data rate. We recommend you use the exact values defined in the DSI86 datasheet. 

Hi  Vishesh,

Thank you for your confirmation.

As I asked before, could you please tell me how much tolerance are anticipated for recommended clock frequency?(12M,19.2M, 26M, 27M, 38.4MHz)

Also could you explain about how much impact is there for DP data rate from REFCLK frequency?
As far as I confirmed, I couldn't found any description as like as correlation between REFCLK and eDP/DSI data rate.

Best regards,
Kazuki Kuramochi

Hi,

We do not have any characterized tolerance for the PLL on the clock. We should be able to lock onto the frequencies of 11.7MHz and 27.18MHz, but these REFCLK frequencies will be multiples up to become the eDP clock which will be embedded into the eDP data.  This slight mismatch will be multiplied up to a larger mismatch between the expected and actual clock. This is why I recommend keeping the exact values defined in the datasheet.

Hi Vishesh,

As I explained, their SoC cannot support required frequency.

Also, you said this device require accurate clock and error will cause huge mismatch due to it is multiplied internally.
But there isn't such a clock which have exactly same frequency against required frequency so your explanation mean every clock has huge mismatch if there isn't any required clock range or method of estimating correlation between clock frequency and data rate.

Could you please provide required frequency range and correlation between frequency and data rate?

Best regards,
Kazuki Kuramochi