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SN65DSI86-Q1: REFCLK tolerance

Kazuki Kuramochi
Genius 11705 points

Part Number: SN65DSI86-Q1

Tool/software:

Hello Expert,

Our customer is designing board using SN65DSI86-Q1 under external REFCLK mode.
This device require 12M,19.2M, 26M, 27M, 38.4MHz REFCLK.
However, customer's SoC can output only 11.7M and 27.18MHz.

Then could you please tell me REFCLK frequency tolerance?

We want to use SoC 11.7M and 27.18MHz signal but there isn't description of acceptable frequency "range".

Best regards,
Kazuki Kuramochi

  • 0
    TI__Guru 55196 points

    Hi,

    I am looking into this and asking the relevant engineers. I will follow up as soon as I have an answer

  • 0 in reply to Vishesh Pithadiya
    TI__Guru 55196 points

    Hi,

    Sorry no update yet. I have sent a follow-up.

  • 0 in reply to Vishesh Pithadiya
    TI__Guru 55196 points

    Hi,

    Just got the update. The DSI86 will be able to latch onto the incoming signal but this will affect the DP data rate. We recommend you use the exact values defined in the DSI86 datasheet. 

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 11705 points

    Hi  Vishesh,

    Thank you for your confirmation.

    As I asked before, could you please tell me how much tolerance are anticipated for recommended clock frequency?(12M,19.2M, 26M, 27M, 38.4MHz)

    Also could you explain about how much impact is there for DP data rate from REFCLK frequency?
    As far as I confirmed, I couldn't found any description as like as correlation between REFCLK and eDP/DSI data rate.

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Guru 55196 points

    Hi,

    We do not have any characterized tolerance for the PLL on the clock. We should be able to lock onto the frequencies of 11.7MHz and 27.18MHz, but these REFCLK frequencies will be multiples up to become the eDP clock which will be embedded into the eDP data.  This slight mismatch will be multiplied up to a larger mismatch between the expected and actual clock. This is why I recommend keeping the exact values defined in the datasheet.

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 11705 points

    Hi Vishesh,

    As I explained, their SoC cannot support required frequency.

    Also, you said this device require accurate clock and error will cause huge mismatch due to it is multiplied internally.
    But there isn't such a clock which have exactly same frequency against required frequency so your explanation mean every clock has huge mismatch if there isn't any required clock range or method of estimating correlation between clock frequency and data rate.

    Could you please provide required frequency range and correlation between frequency and data rate?

    Best regards,
    Kazuki Kuramochi

  • +1 in reply to Kazuki Kuramochi
    TI__Guru 55196 points

    Hi ,

    the tolerance for the PLL is 100ppm. So you will need a signal at 27MHz at 100ppm or 10MHz at 100ppm.

    If you cannot meet this spec, than this device may not perform as expected for eDP outputs.

    Is it possible to add an external oscillator circuit to your design?