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SN65DSI84-Q1: Problem confirmation

Part Number: SN65DSI84-Q1
Other Parts Discussed in Thread: SN65DSI84

Tool/software:

Hi team,

Please clarify the following questions:
1. We see that there are some glitches on the rising and falling edges of the DSI CLK waveform (as shown in the red box in the figure below). Is there a filter or other related circuit inside the SN65DSI84-Q1 to eliminate the impact of this glitches?
Will these glitches affect the sampling of the SN65DSI84-Q1?

2. We see the simulation waveform of SN65DSI84 on TI's official website, but its package is different from that of SN65DSI84-Q1 (not sure what other differences there are).
Can I use the simulation model of SN65DSI84 in the link below to simulate the signal integrity of SN65DSI84-Q1?

https://www.ti.com.cn/product/cn/SN65DSI84#design-tools-simulation

  • HI Alan,

    The DSI84 is a BGA package and the DSI84-Q1 is a QFN package. They will show differences in performance due to the package. It is ok to use the DSI84 IBIS model as a general estimate for the DSI84-Q1 as they have the same die and IO, but this data will not be exact. 

    The glitches seen in the DSI clock waveform should be ok. You may be able to remove these by placing a capacitor between the P and N lanes of the clock. However, these small glitches should not be an issue.

  • Hi Vishesh,

    Thanks for the reply. Since we have confirmed that these glitches will not cause problems, we will not make any changes in this area. We will not add capacitors or anything like that.

    In addition, I would like to ask what is the ability of SN65DSI84-Q1 to suppress glitches? What is the hardware structure of the DSI Receiver of SN65DSI84-Q1? Is there a hysteresis design? Or is there an internal filter?

  • Hi Alan,

    These small glitches will not affect the PLL as they are at too high of a frequency to play a role. In this case the PLL will filter these small glitches out.