DP83867IS: 1588 SFD Pulses

Hi Nicole,

Can you help me understand your system topology?

Are there multiple DP838867 PHYs connected to a single processor?

If TX/RX SFD of multiple PHYs are connected to the same processor GPIO, the processor will not be able to distinguish which PHY is sending the indication pulse.

In the case that the processor needs to know which PHY is sending TX/RX SFD pulses, there should be separate GPIOs allocated for each PHY's SFD pins.

Thank you,

Evan

Hi Evan,

Yes, we are using 18 DP838876 PHYs connected to one processor. It is not necessary to know which PHY is sending the pulse, as long as the pulse can be decoded. What will happen if two PHYs simultaneously send/receive a message?

Hi Nicole,

Are the SFD pulses on a shared bus direct to processor, or using a mux to switch between PHYs?

If it is not required to know which PHY is sending the pulse, I believe this can be achieved using additional components to mux and prevent signal contention.

In the case that SFD pins are routed directly on a shared bus, I'm not clear on what issues could come up during simultaneous transmission.

Thank you,

Evan

Hi Evan, 

That is the part I am unsure about. I have not worked with the SFD pulses before. My limitation is the amount of pins available on my mezzanine connector between the PHYs and processor. 

Using a mux sounds like a good idea, what will be used for the mux select signal? I assume two muxes will be used, one for TX and another for RX, however, the select line can be shared. I am however concerned about the latency that it will introduce. 
Does the TX pulse come from my processor? 

An alternative could be to poll the timestamp registers via MDIO. This can introduce a lot of complexity. I could potentially connect all the interrupt pins of the PHYs together and then at least know when to poll. 

Hi Nicole,

I believe the SFD pulse could also act as the mux select, possibly through some logic components to decide which pulse to send to the processor:

Something to the effect of this logic, but it may become complex considering there are 18 PHYs.

Do you have access to an evaluation board for the processor?

DP83867EVM has breakout jumpers for GPIOs that can be configured for SFD - I'm wondering if we can evaluate the feasibility of multiple SFD pulses driving the line before moving onto more complex HW/SW logic.

Thank you,

Evan

Thank you Evan

Thank you Evan. 

Of course, please reach out for further questions.

Thank you,

Evan